公开(公告)号：US20170338328A1

公开(公告)日：2017-11-23

申请号：US15276784

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E WANG ,  Mark S. RODDER ,  Borna J. OBRADOVIC ,  Dharmendar Reddy PALLE ,  Joon Goo HONG

IPC: H01L29/66 ,  H01L29/04 ,  H01L21/02 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US20170263748A1

公开(公告)日：2017-09-14

申请号：US15276779

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Joon Goo HONG ,  Dharmendar Reddy PALLE ,  Mark S. RODDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

公开(公告)号：US20170263704A1

公开(公告)日：2017-09-14

申请号：US15289951

申请日：2016-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Joon Goo HONG ,  Dharmendar Reddy PALLE ,  Mark S. RODDER

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/786

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

公开(公告)号：US20210057011A1

公开(公告)日：2021-02-25

申请号：US16847741

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan HATCHER ,  Titash RAKSHIT ,  Jorge KITTL ,  Joon Goo HONG ,  Dharmendar PALLE

IPC: G11C11/16 ,  G06F17/17 ,  G06F17/16

Abstract: A method, system and electronic device for mitigating variance in a two transistor two resistive memory element (2T2R) circuit is provided. The method includes calculating a sum of a number of logical 1's in a column of bitcells in the 2T2R circuit, N, of an input vector, sensing output current values from each current line in the column of bitcells and calculating an inner product, M, of the input vector and the bitcells in the column in the 2T2R circuit based on the sensed output current values

公开(公告)号：US20200279176A1

公开(公告)日：2020-09-03

申请号：US16448842

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. HATCHER ,  Titash RAKSHIT ,  Jorge KITTL ,  Rwik SENGUPTA ,  Dharmendar PALLE ,  Joon Goo HONG

IPC: G06N5/04 ,  G11C11/16 ,  G11C13/00 ,  G11C11/22 ,  G06F17/16

Abstract: A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, a third FET and a third resistive memory element connected to a drain of the third FET, and a fourth FET and a fourth resistive memory element connected to a drain of the fourth FET, the drain of the third FET is connected to a gate of the fourth FET and the drain of the fourth FET being connected to a gate of the third FET.

公开(公告)号：US20170110595A1

公开(公告)日：2017-04-20

申请号：US15149722

申请日：2016-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rwik Sengupta ,  Mark Stephen RODDER ,  Joon Goo HONG ,  Titash RAKSHIT

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684

Abstract: A Gate-All-Around (GAA) Field Effect Transistor (FET) can include a horizontal nanosheet conductive channel structure having a width in a horizontal direction in the GAA FET, a height that is perpendicular to the horizontal direction, and a length that extends in the horizontal direction, where the width of the horizontal nanosheet conductive channel structure defines a physical channel width of the GAA FET. First and second source/drain regions can be located at opposing ends of the horizontal nanosheet conductive channel structure and a unitary gate material completely surrounding the horizontal nanosheet conductive channel structure.