公开(公告)号：US20170263704A1

公开(公告)日：2017-09-14

申请号：US15289951

申请日：2016-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Joon Goo HONG ,  Dharmendar Reddy PALLE ,  Mark S. RODDER

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7842 ,  H01L29/786

Abstract: A semiconductor device and a method to form the semiconductor device are disclosed. An n-channel component of the semiconductor device includes a first horizontal nanosheet (hNS) stack and a p-channel component includes a second hNS stack. The first hNS stack includes a first gate structure having a plurality of first gate layers and at least one first channel layer. A first internal spacer is disposed between at least one first gate layer and a first source/drain structure in which the first internal spacer has a first length. The second hNS stack includes a second gate structure having a plurality of second gate layers and at least one second channel layer. A second internal spacer is disposed between at least one second gate layer and a second source/drain structure in which the second internal spacer has a second length that is greater than the first length.

公开(公告)号：US20160035675A1

公开(公告)日：2016-02-04

申请号：US14809266

申请日：2015-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh HEGDE ,  Mark S. RODDER ,  Jorge A. KITTL ,  Robert C. BOWEN

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

Abstract translation: 可以通过在ILD中形成沟槽来形成镶嵌互连结构。 扩散阻挡层可以沉积在沟槽表面上，随后是第一衬里材料。 可以从沟槽的底表面去除第一衬里材料。 第二衬里材料可以定向沉积在底部。 可以在第一和第二衬垫材料上沉积导电种子层，并且导电材料可以填充在沟槽中。 CMP工艺可以从结构的顶部去除多余的材料。 镶嵌互连件可以包括具有沟槽的电介质，布置在沟槽侧壁上的第一衬垫层和布置在沟槽底部上的第二衬垫层。 导电材料可以填充沟槽。 第一衬里材料可以具有低润湿性，并且第二衬里材料相对于导电材料可具有高润湿性。

公开(公告)号：US20170263748A1

公开(公告)日：2017-09-14

申请号：US15276779

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Joon Goo HONG ,  Dharmendar Reddy PALLE ,  Mark S. RODDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods to achieve strained channel finFET devices and resulting finFET devices are presented. In an embodiment, a method for processing a field effect transistor (FET) device may include forming a fin structure comprising a fin channel on a substrate. The method may also include forming a sacrificial epitaxial layer on a side of the fin structure. Additionally, the method may include forming a deep recess in a region that includes at least a portion of the fin structure, wherein the fin structure and sacrificial layer relax to form a strain on the fin channel. The method may also include depositing source/drain (SD) material in the deep recess to preserve the strain on the fin channel.

公开(公告)号：US20170263728A1

公开(公告)日：2017-09-14

申请号：US15267134

申请日：2016-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. KITTL ,  Ganesh HEGDE ,  Robert Christopher BOWEN ,  Borna J. OBRADOVIC ,  Mark S. RODDER

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02485 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7848 ,  H01L29/7853

Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack includes a plurality of sacrificial layers in which each sacrificial layer has a first lattice parameter; and at least one channel layer that has a second lattice parameter in which the first lattice parameter is less than or equal to the second lattice parameter, and each channel layer is disposed between and in contact with two sacrificial layers and includes a compressive strain or a neutral strain based on a difference between the first lattice parameter and the second lattice parameter.