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    SEMICONDUCTOR DEVICE
    21.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180350792A1

    公开(公告)日：2018-12-06

    申请号：US16055728

    申请日：2018-08-06

    Applicant: Renesas Electronics Corporation

    Inventor： Takeshi OKAGAKI ,  Koji SHIBUTANI ,  Makoto YABUUCHI ,  Nobuhiro TSUDA

    IPC: H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L27/0924 ,  H01L29/41791

    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    22.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20180204613A1

    公开(公告)日：2018-07-19

    申请号：US15919525

    申请日：2018-03-13

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto YABUUCHI ,  Hidehiro FUJIWARA

    IPC: G11C11/419 ,  G11C11/417 ,  G11C17/12 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    SEMICONDUCTOR DEVICE
    26.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170301664A1

    公开(公告)日：2017-10-19

    申请号：US15512933

    申请日：2015-03-26

    Applicant: Renesas Electronics Corporation

    Inventor： Yuta YOSHIDA ,  Makoto YABUUCHI ,  Yoshisato YOKOYAMA

    IPC: H01L27/02 ,  H01L27/11 ,  H01L23/528 ,  G11C11/418 ,  H01L23/522 ,  G11C11/419 ,  H01L27/092

    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.

    SEMICONDUCTOR STORAGE DEVICE
    27.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20170092352A1

    公开(公告)日：2017-03-30

    申请号：US15373783

    申请日：2016-12-09

    Applicant: Renesas Electronics Corporation

    Inventor： Toshiaki SANO ,  Ken SHIBATA ,  Shinji TANAKA ,  Makoto YABUUCHI ,  Noriaki MAEDA

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

    Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

    SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA
    28.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA 有权
    用于稳定读取和写入数据的半导体存储器件

    公开(公告)号：US20160172023A1

    公开(公告)日：2016-06-16

    申请号：US15052188

    申请日：2016-02-24

    Applicant: Renesas Electronics Corporation

    Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

    Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

    Abstract translation: 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。

    SEMICONDUCTOR MEMORY
    29.
    发明申请
    SEMICONDUCTOR MEMORY 有权
    半导体存储器

    公开(公告)号：US20150098268A1

    公开(公告)日：2015-04-09

    申请号：US14502660

    申请日：2014-09-30

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Makoto YABUUCHI

    IPC: G11C11/416 ,  G11C8/10 ,  G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/16 ,  G11C11/418

    Abstract: The disclosed invention provides an SRAM capable of stably generating a PUF-ID without having to be powered on/off under control. The SRAM including a plurality of write ports is provided with a plurality of word lines, each transferring write data from each of the write ports to one memory cell. Timing to negate at least two word lines (AWL, BWL), respectively coupled to two write ports, among the word lines is synchronized. Because synchronicity of writing different values to the memory cell is assured, by using a large number of such memory cells, it is possible to stably generate a PUF-ID without power on/off control.

    Abstract translation: 所公开的发明提供了一种能够稳定地产生PUF-ID而不必在控制下通电/断开的SRAM。 包括多个写入端口的SRAM设置有多个字线，每个字线将写入数据从每个写入端口传送到一个存储器单元。 在字线之间分别耦合到两个写入端口的至少两个字线（AWL，BWL）的定时被同步。 由于通过使用大量的这种存储单元来确保向存储单元写入不同值的同步性，所以可以在没有电源开/关控制的情况下稳定地生成PUF-ID。

    SEMICONDUCTOR DEVICE
    30.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220036961A1

    公开(公告)日：2022-02-03

    申请号：US17382923

    申请日：2021-07-22

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shinji TANAKA ,  Yuichiro ISHII ,  Makoto YABUUCHI

    IPC: G11C29/50 ,  G11C11/419 ,  G11C5/06

    Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

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