公开(公告)号：US20230207689A1

公开(公告)日：2023-06-29

申请号：US18174952

申请日：2023-02-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/1608 ,  H01L29/66545 ,  H01L29/66734 ,  H01L21/3086 ,  H01L29/0865 ,  H01L21/046 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/266 ,  H01L29/66068

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US20180166554A1

公开(公告)日：2018-06-14

申请号：US15790195

申请日：2017-10-23

Applicant: Renesas Electronics Corporation

Inventor： Kenichi HISADA ,  Koichi ARAI

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L23/31 ,  H01L29/78 ,  H01L23/29 ,  H01L21/04 ,  H01L21/02

CPC classification number: H01L29/66068 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/045 ,  H01L21/049 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/511 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/7811

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

公开(公告)号：US20180082991A1

公开(公告)日：2018-03-22

申请号：US15824422

申请日：2017-11-28

Applicant: Renesas Electronics Corporation

Inventor： Hisashi TOYODA ,  Koichi YAMAZAKI ,  Koichi ARAI ,  Tatsuhiro SEKI

IPC: H01L25/18 ,  H01L29/10 ,  H03K17/10

CPC classification number: H01L25/18 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L29/1095 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/1207 ,  H01L2924/13062 ,  H01L2924/13091 ,  H02P27/06 ,  H03K17/102 ,  H03K17/6871 ,  H03K17/74 ,  H03K2017/6875 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off MOSFET having a second gate electrode, a second source electrode and a second drain electrode, and a voltage applying unit which applies a voltage to the first gate electrode. The first source electrode of the junction FET is electrically connected to the second drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series, and the voltage applying unit applies a second voltage with a polarity opposite to that of a first voltage applied to the first gate electrode when the junction FET is brought into an off-state, to the first gate electrode when the MOSFET is in an on-state.

公开(公告)号：US20150380541A1

公开(公告)日：2015-12-31

申请号：US14750196

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Masaki HAMA ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

Abstract translation: 本发明可以通过在湿蚀刻上在衬底上打开绝缘膜来指定在SiC衬底上形成的垂直型功率MOSFET的有源区，提高湿式蚀刻的精度​​和使半导体器件的小型化。 在外延层上依次形成膜厚小的氧化硅膜和膜厚度大于氧化硅膜的多晶硅膜，通过干式蚀刻方法打开多晶硅膜，依次将氧化硅膜为 通过湿蚀刻方法打开，从而暴露有源区中的外延层的上表面。

公开(公告)号：US20150214385A1

公开(公告)日：2015-07-30

申请号：US14469799

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI

IPC: H01L29/808 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/66068 ,  H01L21/046 ,  H01L21/8213 ,  H01L21/8232 ,  H01L27/098 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66909 ,  H01L29/8083

Abstract: An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.

Abstract translation: 结FET的导通电阻降低。 在本实施方式的半导体装置中，结场效应晶体管的栅极区域包括低浓度栅极区域和杂质浓度高于低浓度栅极区域的杂质浓度的高浓度栅极区域，高浓度栅极 区域包括在低浓度栅极区域中。

公开(公告)号：US20150035015A1

公开(公告)日：2015-02-05

申请号：US14325614

申请日：2014-07-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koichi ARAI ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/66 ,  H01L29/808

CPC classification number: H01L29/8083 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068

Abstract: To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.

Abstract translation: 提供具有非常优异的截止状态的垂直JFET的半导体器件，而不降低产量。 通过杂质离子注入在源极区的下方形成沿通道宽度方向的截面中四边形的栅极区域。 通过首先蚀刻，去除栅极区域的上表面上方的源极区域以在其间分离。 然后，栅极区域的上表面通过第二蚀刻进行处理，其蚀刻速率在侧表面比栅极区域的中心低。 所得到的栅极区域具有平行于基板表面的下表面和源区域和沟道形成区域之间的边界下方的上表面，并且在沿着沟道宽度方向的横截面中，从侧表面 到中心 结果，可以获得具有减小的变化的通道长度。

公开(公告)号：US20140284625A1

公开(公告)日：2014-09-25

申请号：US14220447

申请日：2014-03-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki KAGOTOSHI ,  Koichi ARAI ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/808 ,  H01L29/66

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。