公开(公告)号：US20200020781A1

公开(公告)日：2020-01-16

申请号：US16578655

申请日：2019-09-23

Applicant: Renesas Electronics Corporation

Inventor： Kenichi HISADA ,  Koichi ARAI

IPC: H01L29/66 ,  H01L23/29 ,  H01L21/02 ,  H01L21/04 ,  H01L29/78 ,  H01L23/31 ,  H01L29/16 ,  H01L29/06

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

公开(公告)号：US20160322227A1

公开(公告)日：2016-11-03

申请号：US15206107

申请日：2016-07-08

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Kenichi HISADA

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p−type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

Abstract translation: 在具有沟槽型MOS栅极结构的碳化硅半导体器件中，本发明使得可以抑制工作特性变化。 通过将p型杂质的角度离子注入施加到通过注入离子而形成的ap型体层而形成具有在沟槽的侧壁处的深度方向上均匀的p型沟道层， 在沟槽形成之后两次或更多次。 此外，虽然当通过成角度的离子注入形成p型沟道层时，p型杂质也被引入到沟槽底部的n型漂移层中，通过形成沟道长度来规定n 杂质浓度高于p型沟道层，p型体层和p型体层与n型漂移层之间的n型漂移层的杂质浓度 。 通过这些措施，可以抑制工作特性的变化。

公开(公告)号：US20160225892A1

公开(公告)日：2016-08-04

申请号：US15095469

申请日：2016-04-11

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Masaki HAMA ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

公开(公告)号：US20150236089A1

公开(公告)日：2015-08-20

申请号：US14706329

申请日：2015-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuaki KAGOTOSHI ,  Koichi ARAI ,  Natsuki YOKOYAMA ,  Haruka SHIMIZU

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808

CPC classification number: H01L29/0619 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/42316 ,  H01L29/66068 ,  H01L29/66893 ,  H01L29/8083

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n−-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n−-type drift layer with a silicon oxide film formed on the n−-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n−-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n−-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract translation: 结型场效应晶体管的制造方法包括以下步骤：（a）在n +型SiC衬底上形成的n型漂移层的表面上形成n +型源极层; （b）通过用形成在用作掩模的n型漂移层上的氧化硅膜蚀刻n型漂移层的表面，形成以预定间隔设置的多个浅沟槽; （c）通过使用垂直离子注入方法通过用氮掺杂每个浅沟槽下方的n型漂移层来形成n型计数器掺杂层; （d）在氧化硅膜和浅沟槽的每个侧壁上形成侧壁间隔物; 和（e）通过使用垂直离子注入法，通过用铝掺杂每个浅沟槽下的n型漂移层来形成p型栅极层。

公开(公告)号：US20230077367A1

公开(公告)日：2023-03-16

申请号：US18057330

申请日：2022-11-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20210028306A1

公开(公告)日：2021-01-28

申请号：US17060486

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI ,  Hironobu MIYAMOTO

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/04 ,  H01L21/02 ,  H01L21/266

Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

公开(公告)号：US20190027597A1

公开(公告)日：2019-01-24

申请号：US16137279

申请日：2018-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasunori YAMASHITA ,  Koichi ARAI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51

Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

公开(公告)号：US20160035904A1

公开(公告)日：2016-02-04

申请号：US14870922

申请日：2015-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi HISADA ,  Koichi ARAI

IPC: H01L29/808 ,  H01L27/098 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/8083 ,  H01L27/098 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66037

Abstract: In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.

Abstract translation: 为了确保杂质扩散率低于硅基的SiC基JFET的性能，确保栅极深度，同时精确地控制栅极区域之间的距离，而不是通过离子注入形成栅极区域到侧壁 的沟渠 这意味着由栅极距离和栅极深度限定的沟道区域应具有高的纵横比。 此外，由于处理的限制，在源极区域内形成栅极区域。 在源极和栅极区域之间形成高度掺杂的PN结导致各种问题，例如结电流的不可避免的增加。 此外，为了形成端接结构，需要显着高能量的离子注入。 在本发明中，提供了一种垂直沟道型SiC功率JFET，其具有位于源极区域之下和栅极区域之下并与源极区分离的浮动栅极区域。

公开(公告)号：US20200161445A1

公开(公告)日：2020-05-21

申请号：US16597600

申请日：2019-10-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Koichi ARAI ,  Nobuo MACHIDA

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/36 ,  H01L29/417

Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.