公开(公告)号：US20210135018A1

公开(公告)日：2021-05-06

申请号：US17121143

申请日：2020-12-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Kenichi HISADA

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US20200161480A1

公开(公告)日：2020-05-21

申请号：US16598832

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Kenichi HISADA

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/47 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US20200020781A1

公开(公告)日：2020-01-16

申请号：US16578655

申请日：2019-09-23

Applicant: Renesas Electronics Corporation

Inventor： Kenichi HISADA ,  Koichi ARAI

IPC: H01L29/66 ,  H01L23/29 ,  H01L21/02 ,  H01L21/04 ,  H01L29/78 ,  H01L23/31 ,  H01L29/16 ,  H01L29/06

Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

公开(公告)号：US20160322227A1

公开(公告)日：2016-11-03

申请号：US15206107

申请日：2016-07-08

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Kenichi HISADA

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/047 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating characteristic from varying. A p-type channel layer having an impurity concentration distribution homogeneous in the depth direction at the sidewall part of a trench is formed by applying angled ion implantation of p-type impurities to a p−type body layer formed by implanting ions having implantation energies different from each other two or more times after the trench is formed. Further, although the p-type impurities are introduced also into an n−-type drift layer at the bottom part of the trench when the p-type channel layer is formed by the angled ion implantation, a channel length is stipulated by forming an n-type layer having an impurity concentration higher than those of the p-type channel layer, the p−-type body layer, and the n−-type drift layer between the p−-type body layer and the n−-type drift layer. By those measures, it is possible to inhibit the operating characteristic from varying.

Abstract translation: 在具有沟槽型MOS栅极结构的碳化硅半导体器件中，本发明使得可以抑制工作特性变化。 通过将p型杂质的角度离子注入施加到通过注入离子而形成的ap型体层而形成具有在沟槽的侧壁处的深度方向上均匀的p型沟道层， 在沟槽形成之后两次或更多次。 此外，虽然当通过成角度的离子注入形成p型沟道层时，p型杂质也被引入到沟槽底部的n型漂移层中，通过形成沟道长度来规定n 杂质浓度高于p型沟道层，p型体层和p型体层与n型漂移层之间的n型漂移层的杂质浓度 。 通过这些措施，可以抑制工作特性的变化。

公开(公告)号：US20160225892A1

公开(公告)日：2016-08-04

申请号：US15095469

申请日：2016-04-11

Applicant: Renesas Electronics Corporation

Inventor： Koichi ARAI ,  Masaki HAMA ,  Yasuaki KAGOTOSHI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/02236 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/049 ,  H01L21/31111 ,  H01L21/32105 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7816

Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.

公开(公告)号：US20230369414A1

公开(公告)日：2023-11-16

申请号：US18358474

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Nobuo MACHIDA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/66734 ,  H01L29/7813

Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

公开(公告)号：US20200161445A1

公开(公告)日：2020-05-21

申请号：US16597600

申请日：2019-10-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Koichi ARAI ,  Nobuo MACHIDA

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/36 ,  H01L29/417

Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.

公开(公告)号：US20190237577A1

公开(公告)日：2019-08-01

申请号：US16223839

申请日：2018-12-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Koichi ARAI ,  Kenichi HISADA ,  Yasunori YAMASHITA ,  Satoshi EGUCHI ,  Hironobu MIYAMOTO ,  Atsushi SAKAI ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/423 ,  H01L29/36 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0274 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66068

Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

公开(公告)号：US20190198663A1

公开(公告)日：2019-06-27

申请号：US16192480

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi SAKAI ,  Katsumi EIKYU ,  Satoshi EGUCHI ,  Nobuo MACHIDA ,  Koichi ARAI ,  Yasuhiro OKAMOTO ,  Kenichi HISADA ,  Yasunori YAMASHITA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0865 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

公开(公告)号：US20170373183A1

公开(公告)日：2017-12-28

申请号：US15627333

申请日：2017-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasunori YAMASHITA ,  Koichi ARAI ,  Kenichi HISADA

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/51 ,  H01L29/45 ,  H01L21/311 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02529 ,  H01L21/31111 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/513 ,  H01L29/66068 ,  H01L29/66734

Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of a part of the gate insulating film part formed on/over a side face of the trench.