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    Compound semiconductor transistor integration with high density capacitor
    22.
    发明授权
    Compound semiconductor transistor integration with high density capacitor 有权

    公开(公告)号：US10026731B1

    公开(公告)日：2018-07-17

    申请号：US15488108

    申请日：2017-04-14

    Applicant: QUALCOMM Incorporated

    Inventor： Bin Yang ,  Xia Li ,  Gengming Tao

    IPC: H01L29/20 ,  H01L27/06 ,  H01L49/02 ,  H01L29/737

    Abstract: A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound semiconductor substrate, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer, and a second dielectric layer on the conductive electrode layer. The MIM capacitor includes a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. A first capacitive component includes the collector contact layer, the conductive electrode layer, and the first dielectric layer. A second capacitive component includes the first conductive interconnect, the conductive electrode layer and the second dielectric layer. A third capacitive component includes the second conductive interconnect, the first conductive interconnect, and the third dielectric layer. The first, second, and third capacitive components are arranged in parallel with each other.

    System and method of programming a memory cell
    25.
    发明授权
    System and method of programming a memory cell 有权
    编程存储器单元的系统和方法

    公开(公告)号：US09373412B2

    公开(公告)日：2016-06-21

    申请号：US14570577

    申请日：2014-12-15

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang

    IPC: G11C5/14 ,  G11C16/30 ,  G11C16/04 ,  G11C5/06 ,  G11C17/18 ,  G11C7/12 ,  G06F17/50 ,  G11C11/40 ,  G11C17/16 ,  G11C11/404

    CPC classification number: G11C17/18 ,  G06F17/5045 ,  G11C5/06 ,  G11C5/146 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C11/5692 ,  G11C16/04 ,  G11C17/16 ,  G11C2211/4016

    Abstract: An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.

    Abstract translation: 一种装置包括半导体晶体管结构。 半导体晶体管结构包括电介质材料，沟道区，栅极，源极重叠区域和漏极重叠区域。 源重叠区域是可偏置的，以使源重叠区域和栅极之间的第一电压差超过电介质材料的击穿电压。 漏极重叠区域是可偏置的，以使漏极重叠区域和栅极之间的第二电压差超过击穿电压。 该装置包括耦合到半导体晶体管的本体的阱线。 该装置包括被配置为向阱管线施加电压以防止沟道区域和栅极之间的击穿状态的电路。

    Complementary back end of line (BEOL) capacitor
    26.
    发明授权
    Complementary back end of line (BEOL) capacitor 有权
    互补后端（BEOL）电容

    公开(公告)号：US09252104B2

    公开(公告)日：2016-02-02

    申请号：US14512191

    申请日：2014-10-10

    Applicant: QUALCOMM INCORPORATED

    Inventor： John J. Zhu ,  Bin Yang ,  Pr Chidambaram ,  Lixin Ge ,  Jihong Choi

    IPC: H01L29/00 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

    CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

    Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。 此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。

    FIN-TYPE SEMICONDUCTOR DEVICE
    28.
    发明申请
    FIN-TYPE SEMICONDUCTOR DEVICE 有权
    FIN型半导体器件

    公开(公告)号：US20150187774A1

    公开(公告)日：2015-07-02

    申请号：US14659893

    申请日：2015-03-17

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Bin Yang ,  Stanley Seungchul Song

    IPC: H01L27/092 ,  H01L29/06 ,  G06F17/50 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10

    CPC classification number: H01L27/0924 ,  G06F17/5045 ,  G06F17/5068 ,  H01L21/265 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0607 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: An apparatus comprises a substrate and a fin-type semiconductor device extending from the substrate. The fin-type semiconductor device comprises means for providing a first fin-type conduction channel having first and second regions, means for providing a second fin-type conduction channel having a fourth region above a third region, and means for shielding current leakage coupled to at least one of the first region and the third region. The first region has a first doping concentration greater than a second doping concentration of the second region. The first fin-type conduction channel comprises first ion implants implanted into the substrate at a first depth and second ion implants implanted into the substrate at a different depth. The third region has a third doping concentration, and the fourth region has a fourth doping concentration.

    Abstract translation: 一种装置包括从衬底延伸的衬底和鳍式半导体器件。 翅片型半导体器件包括用于提供具有第一和第二区域的第一鳍式传导沟道的装置，用于提供具有在第三区域上方的第四区域的第二鳍式传导沟道的装置，以及用于屏蔽漏电耦合到 第一区域和第三区域中的至少一个。 第一区域具有大于第二区域的第二掺杂浓度的第一掺杂浓度。 第一鳍型传导通道包括在第一深度处植入衬底中的第一离子植入物和在不同深度处植入衬底中的第二离子植入物。 第三区域具有第三掺杂浓度，第四区域具有第四掺杂浓度。

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