Semiconductor device having a thick strained silicon layer and method of its formation
    21.
    发明授权
    Semiconductor device having a thick strained silicon layer and method of its formation 有权
    具有厚的应变硅层的半导体器件及其形成方法

    公开(公告)号:US06902991B2

    公开(公告)日:2005-06-07

    申请号:US10282513

    申请日:2002-10-24

    摘要: A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.

    摘要翻译: 在硅锗层上生长应变硅层,并且在单个连续原位沉积工艺中,在应变硅层上生长第二层硅锗。 硅锗的两层可以用应变硅原位生长。 这种结构在应变硅层的两侧有效地提供了两个基板,以支撑应变硅层的拉伸应变,并且抵抗可能在加工过程中温度变化引起的失配位错的形成。 因此,可以在具有给定锗含量的衬底上生长的应变硅的临界厚度被有效地加倍。 覆盖应变硅层的硅锗层可以在MOSFET加工过程中保持,以抵抗在形成栅极绝缘材料时产生应变硅层中的失配位错。

    METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FOM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE
    22.
    发明申请
    METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FOM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 有权
    具有不同工作功能的金属的方法用于具有高K栅介质和相关结构的FOM CMOS栅

    公开(公告)号:US20050054149A1

    公开(公告)日:2005-03-10

    申请号:US10654689

    申请日:2003-09-04

    摘要: According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

    摘要翻译: 根据一个示例性实施例,一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。 该方法还包括在电介质层上沉积第一金属层。 该方法还包括在第一金属层上沉积第二金属层。 该方法还包括在衬底的NMOS区域中注入氮气,并将第一金属层的第一部分转变为金属氧化物层,并将第一金属层的第二部分转换为金属氮化物层。 该方法还包括形成NMOS栅极和PMOS栅极,其中NMOS栅极包括一段金属氮化物层,PMOS栅极包括金属氧化物层的一段。

    Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication
    23.
    发明授权
    Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication 有权
    具有改善的源极/漏极延伸掺杂剂扩散电阻的应变硅MOSFET及其制造方法

    公开(公告)号:US06756276B1

    公开(公告)日:2004-06-29

    申请号:US10335522

    申请日:2002-12-31

    IPC分类号: H01L21336

    摘要: An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

    摘要翻译: 在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET(NMOS)。 MOSFET包括形成在应变硅层中的第一晕圈,其范围朝向超过浅源极和漏极延伸端的沟道区域。 形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区,并且比浅源极和漏极延伸部更深地延伸到硅锗层中。 第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。 通过以这种方式抵消增加的n型掺杂剂的扩散速率,维持浅的源极和漏极延伸分布,并且降低由短沟道效应引起的退化的风险。

    CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric
    24.
    发明授权
    CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric 有权
    通过集成具有不同功函数并且具有高k栅极电介质的金属形成的CMOS栅极

    公开(公告)号:US07176531B1

    公开(公告)日:2007-02-13

    申请号:US11020990

    申请日:2004-12-22

    IPC分类号: H01L29/76

    摘要: According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

    摘要翻译: 根据一个示例性实施例,一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。 该方法还包括在电介质层上沉积第一金属层。 该方法还包括在第一金属层上沉积第二金属层。 该方法还包括在衬底的NMOS区域中注入氮气,并将第一金属层的第一部分转变为金属氧化物层,并将第一金属层的第二部分转换为金属氮化物层。 该方法还包括形成NMOS栅极和PMOS栅极,其中NMOS栅极包括金属氮化物层的一部分,PMOS栅极包括金属氧化物层的一部分。

    Strained silicon MOSFET having improved thermal conductivity and method for its fabrication
    25.
    发明授权
    Strained silicon MOSFET having improved thermal conductivity and method for its fabrication 失效
    具有改进的导热性的应变硅MOSFET及其制造方法

    公开(公告)号:US07012007B1

    公开(公告)日:2006-03-14

    申请号:US10658479

    申请日:2003-09-09

    IPC分类号: H01L21/336

    摘要: A strained silicon MOSFET employs a high thermal conductivity insulating material in the trench isolations to dissipate thermal energy generated in the MOSFET and to avoid self-heating caused by the poor thermal conductivity of an underlying silicon germanium layer. The high thermal conductivity material is preferably silicon carbide, and the isolations preferably extend through the silicon germanium layer to contact an underlying silicon layer so as to conduct thermal energy from the active region to the silicon layer.

    摘要翻译: 应变硅MOSFET在沟槽隔离中采用高导热绝缘材料,以消散MOSFET中产生的热能,并避免由于下层硅锗层导热性差导致的自发热。 高导热性材料优选为碳化硅,并且隔离优选延伸穿过硅锗层以接触下面的硅层,以便将热能从有源区传导到硅层。

    Field effect transistor having increased carrier mobility
    27.
    发明申请
    Field effect transistor having increased carrier mobility 有权
    场效应晶体管具有增加的载流子迁移率

    公开(公告)号:US20050040477A1

    公开(公告)日:2005-02-24

    申请号:US10643461

    申请日:2003-08-18

    摘要: According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

    摘要翻译: 根据一个示例性实施例,位于衬底上方的FET包括位于衬底中的通道。 FET还包括位于沟道上方的第一栅极电介质,其中第一栅极电介质具有第一热膨胀系数。 FET还包括位于第一栅极电介质上方的第一栅电极,其中第一栅电极具有第二热膨胀系数,并且其中第二热膨胀系数不同于第一热膨胀系数,从而导致 增加FET中的载流子迁移率。 例如,第二热膨胀系数可以大于第一热膨胀系数。 载流子迁移率的增加可以由例如在通道中产生的拉伸应变引起。