公开(公告)号：US20150303148A1

公开(公告)日：2015-10-22

申请号：US14254764

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Chengjie Zuo ,  Changhan Hobie Yun ,  David Francis Berdy ,  Robert Paul Mikulka

IPC: H01L23/552 ,  H01L23/00 ,  H05K9/00 ,  H01L23/04 ,  H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/32 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01R12/7076 ,  H01R12/714 ,  H05K1/181 ,  H05K9/0032 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.

Abstract translation: 一些新颖特征涉及包括封装衬底，管芯，封装层和第一组金属层的集成器件封装（例如管芯封装）。 封装衬底包括第一表面和第二表面。 管芯耦合到封装衬底的第一表面。 封装层封装模具。 第一组金属层耦合到封装层的第一外表面。 在一些实施方案中，第一组金属层被配置为作为集成器件封装的管芯到线连接器工作。 在一些实施方案中，集成器件封装包括耦合到封装衬底的第二表面的第二组金属层。 在一些实施方案中，集成器件封装包括耦合到封装层的第二外表面的第二组金属层。

公开(公告)号：US09041212B2

公开(公告)日：2015-05-26

申请号：US13787476

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Dong Wook Kim ,  Victor Adrian Chiriac ,  Kyu-Pyung Hwang ,  Changhan Hobie Yun ,  Young Kyu Song

IPC: H01L23/48 ,  H01L23/34 ,  H01L23/367 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor package structure that includes a package substrate, a first package, an interposer coupled to the first package, and a first set of through via insert (TVI). The first set of TVI is coupled to the interposer and the package substrate. The first set of TVI is configured to provide heat dissipation from the first package. In some implementations, the semiconductor package structure further includes a heat spreader coupled to the interposer. The heat spreader is configured to dissipate heat from the first package. In some implementations, the first set of TVI is further configured to provide an electrical path between the first package and the package substrate. In some implementations, the first package is electrically coupled to the package substrate through the interposer and the first set of TVI. In some implementations, the first set of TVI includes a dielectric layer and a metal layer.

Abstract translation: 一些实施方案提供半导体封装结构，其包括封装衬底，第一封装，耦合到第一封装的插入器和第一组通孔插入件（TVI）。 第一组TVI耦合到插入器和封装衬底。 第一组TVI被配置为提供第一包装的散热。 在一些实施方案中，半导体封装结构还包括耦合到插入件的散热器。 散热器被配置为从第一包装散发热量。 在一些实施方式中，第一组TVI被进一步配置成在第一封装和封装衬底之间提供电路径。 在一些实施方案中，第一封装通过插入器和第一组TVI电耦合到封装衬底。 在一些实施方案中，第一组TVI包括电介质层和金属层。

公开(公告)号：US20150048480A1

公开(公告)日：2015-02-19

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US20140132297A1

公开(公告)日：2014-05-15

申请号：US13675673

申请日：2012-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： Kyu-Pyung Hwang ,  Young K. Song ,  Changhan Hobie Yun ,  Dong Wook Kim

IPC: G01R1/07

CPC classification number: G01R1/07 ,  G01R31/002

Abstract: Systems and methods for EMC, EMI and ESD testing are described. A probe comprises a center conductor extending along an axis of the probe, a probe tip, and a shield coaxially aligned with the center conductor and configured to provide electromagnetic screening for the probe tip. One or more actuators may change the relative positions of the probe tip and shield with respect to a device under test, thereby enabling control of sensitivity and resolution of the probe.

Abstract translation: 描述了用于EMC，EMI和ESD测试的系统和方法。 探针包括沿着探针的轴线延伸的中心导体，探针尖端和与中心导体同轴对准的屏蔽并且被配置为为探针尖端提供电磁屏蔽。 一个或多个致动器可以相对于被测器件改变探头尖端和屏蔽件的相对位置，从而能够控制探头的灵敏度和分辨率。

公开(公告)号：US20220246552A1

公开(公告)日：2022-08-04

申请号：US17166430

申请日：2021-02-03

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Daniel Daeik Kim ,  Paragkumar Ajaybhai Thadesar ,  Nosun Park ,  Sameer Sunil Vadhavkar

IPC: H01L23/66 ,  H01L23/64 ,  H01L49/02

Abstract: Mobile phones and other mobile devices communicate wirelessly by transmitting and receiving RF signals. Transmitters and receivers in wireless devices process RF signals in certain frequency ranges or bands. Signals in other frequencies can be blocked or filtered out by, for example, a lumped-element circuit or a lumped-element filter consisting of passive electrical components such as inductors, capacitors, and resistors. A passive component device, or integrated passive device, is one example of a lumped-element filter fabricated with passive components on a die. In a mobile device, a passive component device and one or more integrated circuits or other chips used for signal processing are interconnected by being mounted on (i.e., coupled to) a metallization structure or package substrate in a chip module or multi-chip module. The demand for miniaturization of hand-held mobile devices drives a need for reducing the sizes of chip modules that are inside a mobile device.

公开(公告)号：US11239158B1

公开(公告)日：2022-02-01

申请号：US17066154

申请日：2020-10-08

Applicant: QUALCOMM Incorporated

Inventor： Paragkumar Ajaybhai Thadesar ,  Changhan Hobie Yun ,  Sameer Sunil Vadhavkar ,  Daniel Daeik Kim ,  Francesco Carrara

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/00

Abstract: An integrated circuit (IC) package comprising a first die, including an active layer opposite a backside surface of the first die supporting a plurality of backside pads is provided. The IC package also incorporates a package substrate coupled to the active layer. The package pads on the package substrate correspond to the plurality of backside pads. A passive device comprising a plurality of wire bonds is coupled to the plurality of backside pads and the plurality of package pads. The passive device may also comprise a plurality of wire bonds coupled to the package pads by through silicon vias (TSVs). Multiple dies may be coupled with die-to-die wire bonds coupled to backside pads on each die.

公开(公告)号：US10903240B2

公开(公告)日：2021-01-26

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daniel Daeik Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L23/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US10693432B2

公开(公告)日：2020-06-23

申请号：US15982655

申请日：2018-05-17

Applicant: QUALCOMM Incorporated

Inventor： Nosun Park ,  Changhan Hobie Yun ,  Jonghae Kim ,  Niranjan Sunil Mudakatte ,  Xiaoju Yu ,  Wei-Chuan Chen

IPC: H03H7/01 ,  H01F27/40 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L27/01 ,  H01L49/02 ,  H03H1/00 ,  H03H3/00

Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.

公开(公告)号：US10187031B2

公开(公告)日：2019-01-22

申请号：US15151351

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H7/38 ,  H03H7/40 ,  H04B1/04

Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.

公开(公告)号：US10074625B2

公开(公告)日：2018-09-11

申请号：US14859323

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco Velez ,  David Francis Berdy ,  Changhan Hobie Yun ,  Jonghae Kim ,  Chengjie Zuo ,  Daeik Daniel Kim ,  Je-Hsiung Jeffrey Lan ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0905

Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.