Driver IC for use with simple microcontrol
    23.
    发明申请
    Driver IC for use with simple microcontrol 有权
    驱动IC用于简单的微控制

    公开(公告)号:US20040032288A1

    公开(公告)日:2004-02-19

    申请号:US10618487

    申请日:2003-07-11

    Inventor: Peter Green

    CPC classification number: H03K17/08122 H03K17/6871

    Abstract: A driver circuit for driving a switching circuit driving a load, e.g., a gas discharge lamp, the drive circuit comprising an input trigger circuit receiving a pulsed input signal for controlling the generation of two drive signals, a first drive signal driving a high side switch of a half bridge switching circuit and a second drive signal driving a low side switch of the half bridge switching circuit, a circuit for providing a dead time between the first and second drive signals whereby both the first and second drive signals are substantially zero, the input trigger circuit generating a control signal for controlling the generation of the first and second drive signals based on a characteristic of the pulsed input signal and first and second drive circuits for providing the first and second drive signals.

    Abstract translation: 一种用于驱动驱动负载的开关电路(例如气体放电灯)的驱动电路,所述驱动电路包括接收用于控制两个驱动信号的产生的脉冲输入信号的输入触发电路,驱动高侧开关的第一驱动信号 半桥开关电路和驱动半桥开关电路的低侧开关的第二驱动信号的电路,用于在第一和第二驱动信号之间提供死区时间的电路,由此第一和第二驱动信号都基本为零, 输入触发电路,其基于脉冲输入信号的特性和用于提供第一和第二驱动信号的第一和第二驱动电路产生用于控制第一和第二驱动信号的产生的控制信号。

    Active filter for reduction of common mode current

    公开(公告)号:US20040004514A1

    公开(公告)日:2004-01-08

    申请号:US10609273

    申请日:2003-06-26

    Inventor: Brian R. Pelly

    Abstract: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load, said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus, a PWM inverter having input terminals coupled to said positive d-c bus and negative d-c bus and having a controlled a-c output, a load driven by said a-c output of said PWM inverter, a ground wire extending from said load, and a current sensor for measuring the common mode current in said drive circuit in said ground wire, said current sensor producing an output current related to said common mode current, said active filter comprising a first and second MOSFET transistor, each having first and second main electrodes and a control electrode, and an amplifier driving a respective one of the transistors; said first electrode of said first and second transistor coupled to a common node, said second electrodes of said first and second transistors being coupled to said positive d-c bus and said negative d-c respectively; each of said amplifiers having an input coupled to said output of said current sensor and each having an output connected to a respective one of said control electrodes; and a d-c isolating capacitor connecting said common node of said first electrode of said first and second transistors to said ground wire.

    Anti-pinch window drive circuit
    25.
    发明申请
    Anti-pinch window drive circuit 有权
    防夹窗驱动电路

    公开(公告)号:US20030137265A1

    公开(公告)日:2003-07-24

    申请号:US10348682

    申请日:2003-01-21

    Inventor: Xavier de Frutos

    CPC classification number: H02H7/0851 H02H7/093

    Abstract: An antipinch circuit prevents the motor driven closure of an automotive window if a soft obstacle is compressed between the window and the top of the door frame, and the window is opened in response to the sensing of the obstacle. The circuit measures the motor torque (by measuring motor current) and the motor shaft speed (by measuring motor back EMF). The torque and motor speed are compared to nullsignaturesnull of these values in the case of the window closing normally against the top of the door frame, or against an obstacle, and either stopping or reversing the motor rotation accordingly.

    Abstract translation: 如果在窗户和门框的顶部之间压缩了软障碍物,则响应于障碍物的感测而打开窗户,止反电路可以防止汽车窗的马达驱动关闭。 电路测量电机转矩(通过测量电机电流)和电机轴转速(通过测量电机反电动势)。 在窗口正常关闭门框顶部或障碍物的情况下,扭矩和电机速度与这些值的“签名”进行比较,并且相应地停止或反转电机旋转。

    Low cost fast recovery diode and process of its manufacture
    27.
    发明申请
    Low cost fast recovery diode and process of its manufacture 审中-公开
    低成本快速恢复二极管及其制造工艺

    公开(公告)号:US20020195613A1

    公开(公告)日:2002-12-26

    申请号:US10115757

    申请日:2002-04-02

    CPC classification number: H01L29/402 H01L29/32 H01L29/66136 H01L29/8611

    Abstract: A fast recovery diode has a single large area P/N junction surrounded by a termination region. The anode contact in contact with the central active area extends over the inner periphery of an oxide termination ring and an EQR metal ring extends over the outer periphery of the oxide termination ring. Platinum atoms are diffused into the back surface of the device. A three mask process is described. An amorphous silicon layer is added in a four mask process, and a plurality of spaced guard rings are added in a five mask process.

    Abstract translation: 快速恢复二极管具有由终端区域包围的单个大面积P / N结。 与中心有源区接触的阳极触点在氧化物终止环的内周边延伸,并且EQR金属环在氧化物终止环的外周延伸。 铂原子扩散到器件的后表面。 描述三个掩模过程。 在四掩模工艺中添加非晶硅层,并且在五个掩模工艺中添加多个间隔保护环。

    Reversed source-drain mosgated device
    29.
    发明申请
    Reversed source-drain mosgated device 有权
    反向源极漏极mosgated器件

    公开(公告)号:US20020036318A1

    公开(公告)日:2002-03-28

    申请号:US09907262

    申请日:2001-07-17

    Inventor: Naresh Thapar

    CPC classification number: H01L29/781 H01L29/7827

    Abstract: A MOSgated device with a minimum overlap between the gate and drain electrodes is comprised of an Nnull substrate which receives an epitaxial layer of silicon. The body of the epitaxial layer has an N- lower layer for an accumulation device or a Pnull drift lower layer. In each case the top of the epitixial layer is Nnull. Both can be operated in an a-c mode. A trench gate consists of a trench through the epitaxial layer which has a thin gate oxide layer on its walls and bottom and a conductive polysilicon gate body filling the trench. The thin oxide on the bottom of the trench may be thicker than the oxide on the walls to reduce gate capacitance. A thick isolation oxide which is about 10 times as thick as the gate oxide overlies the top of the polysilicon. A planar drain electrode overlies the Nnull top layer and the laterally spaced isolation oxide; and a planar source electrode contacts the bottom of the substrate.

    Abstract translation: 栅极和漏极之间具有最小重叠的MOS器件由接纳硅外延层的N +衬底构成。 外延层的主体具有用于累积装置或P-漂移下层的N-下层。 在每种情况下,上皮层的顶部是N +。 两者都可以在a-c模式下操作。 沟槽栅由通过外延层的沟槽组成,其沟槽在其壁和底部具有薄的栅极氧化物层,以及填充沟槽的导电多晶硅栅极体。 沟槽底部的薄氧化物可以比壁上的氧化物厚,以减小栅极电容。 厚度约为栅极氧化物厚度的10倍的厚隔离氧化物覆盖多晶硅的顶部。 平面漏极覆盖在N +顶层和横向隔开的隔离氧化物上; 并且平面源电极接触衬底的底部。

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