公开(公告)号：US11916782B2

公开(公告)日：2024-02-27

申请号：US17594782

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jonathan P. Beecroft ,  Abdulla M. Bataineh ,  Thomas L. Court ,  David Charles Hewson

IPC: H04L45/28 ,  H04L45/02 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/02 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A data-driven intelligent networking system that can facilitate global fairness is provided. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and enforce global fairness on a per-flow basis.

公开(公告)号：US20240039836A1

公开(公告)日：2024-02-01

申请号：US18479755

申请日：2023-10-02

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Duncan Roweth ,  Edwin L. Froese ,  Joseph G. Kopnick ,  Andrew S. Kopser ,  Robert Alverson

IPC: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625

CPC classification number: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/22 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/30 ,  H04L69/40 ,  H04L47/39 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/1673 ,  G06F13/1689 ,  H04L45/021 ,  H04L45/38 ,  H04L47/12 ,  G06F13/1642 ,  G06F13/4221 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/621 ,  H04L47/24 ,  H04L49/9021 ,  G06F13/16 ,  G06F13/385 ,  G06F13/4022 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L45/123 ,  H04L47/122 ,  H04L45/566 ,  G06F12/1036 ,  G06F15/17331 ,  H04L49/90 ,  H04L43/10 ,  H04L45/20 ,  H04L45/42 ,  H04L47/11 ,  H04L47/18 ,  G06F12/0862 ,  G06F12/1063 ,  H04L47/323 ,  G06F9/546 ,  G06F13/14 ,  G06F9/505 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  G06F13/4068 ,  H04L47/6235 ,  H04L47/762 ,  H04L47/781 ,  H04L47/20 ,  H04L49/9036 ,  H04L49/9047 ,  H04L1/0083 ,  H04L43/0876 ,  H04L45/46 ,  H04L45/70 ,  H04L47/2466 ,  H04L47/626 ,  H04L47/32 ,  G06F2213/0026 ,  G06F2213/3808 ,  G06F2212/50 ,  H04L69/28

Abstract: Systems and methods are provided for passing data amongst a plurality of switches having a plurality of links attached between the plurality of switches. At a switch, a plurality of load signals are received from a plurality of neighboring switches. Each of the plurality of load signals are made up of a set of values indicative of a load at each of the plurality of neighboring switches providing the load signal. Each value within the set of values provides an indication for each link of the plurality of links attached thereto as to whether the link is busy or quiet. Based upon the plurality of load signals, an output link for routing a received packet is selected, and the received packet is routed via the selected output link.

公开(公告)号：US20230418763A1

公开(公告)日：2023-12-28

申请号：US18203186

申请日：2023-05-30

Applicant: SiFive, Inc.

Inventor： Benoy Alexander ,  John Ingalls ,  Mohit Gopal Wani

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F2212/681 ,  G06F2212/684

Abstract: Described is a translation lookaside buffer (TLB) prefetcher with multi-level TLB prefetches and feedback architecture. A processing system includes two or more translation lookaside buffer (TLB) levels, each TLB level including a miss queue, and a TLB prefetcher connected to each of the two or more TLB levels. The TLB prefetcher configured to receive feedback from the miss queue at each TLB level for previously sent TLB prefetches and control number of TLB prefetches sent for a trained TLB entry to each TLB level of the two or more TLB levels based on the feedback.

公开(公告)号：US11853227B2

公开(公告)日：2023-12-26

申请号：US17242729

申请日：2021-04-28

Applicant: Arm Limited

Inventor： Charles Andrew Giefer ,  Alexander Donald Charles Chadwick

IPC: G06F12/10 ,  G06F12/1045 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/1036

CPC classification number: G06F12/1045 ,  G06F12/0238 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F12/1063 ,  G06F2212/651 ,  G06F2212/653 ,  G06F2212/7201

Abstract: There is provided a data processing apparatus and method of data processing. The data processing apparatus comprises storage circuitry to store a hierarchy of page tables comprising an intermediate level page table. Each entry of the intermediate level page table comprises base address information of a next level page table and control information indicating whether an addressing function has been applied to reorder physical storage locations of entries of the next level page table. Address translation circuitry is provided to perform address translations in response to receipt of a virtual address by performing a lookup in a next level page table dependent on the base address information and a page table index from the virtual address. When the control information indicates that the addressing function has been applied, the lookup is performed at a modified storage location generated by applying the addressing function to the page table index.

公开(公告)号：US20230401159A1

公开(公告)日：2023-12-14

申请号：US18455479

申请日：2023-08-24

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F12/1036 ,  G06F12/08 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

CPC classification number: G06F12/1036 ,  G06F12/08 ,  G06F12/0646 ,  G06F12/0284 ,  G06F12/109 ,  G06F12/10

Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

公开(公告)号：US20230396533A1

公开(公告)日：2023-12-07

申请号：US18454860

申请日：2023-08-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Jonathan P. Beecroft

IPC: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625

CPC classification number: H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/22 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/30 ,  H04L69/40 ,  H04L47/39 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/1673 ,  G06F13/1689 ,  H04L45/021 ,  H04L45/38 ,  H04L47/12 ,  G06F13/1642 ,  G06F13/4221 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/621 ,  H04L47/24 ,  H04L49/9021 ,  G06F13/16 ,  G06F13/385 ,  G06F13/4022 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L45/123 ,  H04L47/122 ,  H04L45/566 ,  G06F12/1036 ,  G06F15/17331 ,  H04L49/90 ,  H04L43/10 ,  H04L45/20 ,  H04L45/42 ,  H04L47/11 ,  H04L47/18 ,  G06F12/0862 ,  G06F12/1063 ,  H04L47/323 ,  G06F9/546 ,  G06F13/14 ,  G06F9/505 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  G06F13/4068 ,  H04L47/6235 ,  H04L47/762 ,  H04L47/781 ,  H04L47/20 ,  H04L49/9036 ,  H04L49/9047 ,  H04L1/0083 ,  H04L43/0876 ,  H04L45/46 ,  H04L45/70 ,  H04L47/2466 ,  H04L47/626 ,  H04L47/32 ,  G06F2213/0026 ,  G06F2213/3808 ,  G06F2212/50 ,  H04L69/28

Abstract: Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.

公开(公告)号：US11757763B2

公开(公告)日：2023-09-12

申请号：US17594647

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Igor Gorodetsky ,  Hess M. Hodge ,  Timothy J. Johnson

IPC: G06F13/42 ,  H04L45/28 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F13/14 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

公开(公告)号：US11748302B2

公开(公告)日：2023-09-05

申请号：US17561427

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/0831

CPC classification number: G06F16/13 ,  G06F9/30 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/461 ,  G06F16/113 ,  G06F16/172 ,  G06F12/0831 ,  G06F12/1036 ,  G06F12/1045 ,  G06F2201/84

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230195650A1

公开(公告)日：2023-06-22

申请号：US18170093

申请日：2023-02-16

Applicant: Red Hat, Inc.

Inventor： Gal Hammer ,  Marcel Apfelbaum

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/06 ,  G06F9/455 ,  G06F12/1072

CPC classification number: G06F12/1036 ,  G06F12/1009 ,  G06F12/0646 ,  G06F9/45558 ,  G06F12/1072 ,  G06F2009/45583

Abstract: Disclosed is a method of managing memory of a virtual machine (VM), including providing a physical IOMMU device on a host, and performing a memory translation using the physical IOMMU device on the host.

公开(公告)号：US20230082195A1

公开(公告)日：2023-03-16

申请号：US17475229

申请日：2021-09-14

Applicant: Red Hat, Inc.

Inventor： Gal Hammer ,  Marcel Apfelbaum

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/1072 ,  G06F12/06 ,  G06F9/455

Abstract: Disclosed is a method of managing memory of a virtual machine (VM), including receiving, at a physical input-output memory management unit (IOMMU) of a processing device operating the VM, a request from a VM IOMMU for VM memory address translation for a VM peripheral component interconnect (PCI) device created on the VM; determining, by the physical IOMMU, a corresponding VM memory address translation result based on the request as received and a memory translation table; and transmitting, by the physical IOMMU to the VM IOMMU, the corresponding VM memory address translation result for servicing the request for VM memory address translation of the VM PCI device.