公开(公告)号：US3996077A

公开(公告)日：1976-12-07

申请号：US552976

申请日：1975-02-26

申请人： Wilhelmus Henricus Cornelis Gerardus Verkuijlen

发明人： Wilhelmus Henricus Cornelis Gerardus Verkuijlen

IPC分类号： H01L21/76 ,  H01L21/22 ,  H01L21/32 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73

CPC分类号： H01L21/762 ,  H01L21/32 ,  H01L21/76202 ,  Y10S148/037 ,  Y10S148/043 ,  Y10S148/085

摘要： A method of manufacturing a semiconductor device, comprising the steps of providing a semiconductor body comprising a first surface and an underlying semiconductor portion that is of first conductivity type, providing a doping material of said first conductivity type at a first portion of said first surface prior to the formation of a sunken insulating layer, said first portion being situated beside said sunken insulation layer, forming an insulation layer consisting of insulating material and sunk locally in said body from said first surface, and then introducing said doping material into said semiconductor body via said first portion of said first surface so as to form a zone of said first conductivity type, said zone contacting said underlying semiconductor portion, and zone extending at the area of contact to a depth greater than that of said sunken insulation layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：提供包括第一表面和第一导电类型的下面的半导体部分的半导体本体，在所述第一表面的第一部分提供所述第一导电类型的掺杂材料， 形成凹陷绝缘层，所述第一部分位于所述凹陷绝缘层的旁边，形成由绝缘材料构成的绝缘层，并从所述第一表面在所述主体中局部沉没，然后将所述掺杂材料引入所述半导体本体中， 所述第一表面的所述第一部分形成所述第一导电类型的区域，所述区域接触所述下面的半导体部分，以及在所述接触区域处延伸的深度大于所述凹陷绝缘层的深度。

公开(公告)号：US3977920A

公开(公告)日：1976-08-31

申请号：US500067

申请日：1974-08-23

申请人： Ichiro Imaizumi ,  Tadao Kaji ,  Akio Hayasaka ,  Keijiro Uehara

发明人： Ichiro Imaizumi ,  Tadao Kaji ,  Akio Hayasaka ,  Keijiro Uehara

IPC分类号： H01L21/033 ,  H01L29/735 ,  H01L21/22

CPC分类号： H01L21/033 ,  H01L29/735 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/106 ,  Y10S148/114 ,  Y10S148/167

摘要： A lateral transistor or the like is made by the steps of forming a first insulating layer on a semiconductor substrate and providing a first hole in this insulating layer so as to expose a first surface portion of the substrate. An impurity of a first conductivity type is introduced through the hole and a second hole is formed in the insulating layer so as to expose a second surface portion of the substrate spaced apart from the first portion. Then, a second insulating layer of a material different from that of the first layer is formed on the first insulating layer and on the first and second surface portions of the substrate. Subsequently, third and fourth holes are formed in the second insulating layer within the confines of these holes to expose at least portions of the first and second surface portions of the substrate. Then, an impurity of a second conductivity type is introduced into the exposed first and second surface portions of the substrate through the third and fourth holes.

摘要翻译： 横向晶体管等通过在半导体衬底上形成第一绝缘层并在该绝缘层中提供第一孔以暴露衬底的第一表面部分的步骤制成。 通过孔引入第一导电类型的杂质，并且在绝缘层中形成第二孔，以暴露基板与第一部分间隔开的第二表面部分。 然后，在第一绝缘层和基板的第一和第二表面部分上形成与第一层不同的材料的第二绝缘层。 随后，在这些孔的范围内的第二绝缘层中形成第三和第四孔，以暴露基板的第一和第二表面部分的至少一部分。 然后，通过第三孔和第四孔将第二导电类型的杂质引入到基板的暴露的第一和第二表面部分中。

公开(公告)号：US3961999A

公开(公告)日：1976-06-08

申请号：US592015

申请日：1975-06-30

申请人： Igor Antipov

发明人： Igor Antipov

IPC分类号： H01L21/76 ,  H01L21/00 ,  H01L21/762 ,  H01L21/20

CPC分类号： H01L21/76227 ,  H01L21/00 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/114 ,  Y10S148/117 ,  Y10S148/122 ,  Y10S148/151 ,  Y10S438/969

摘要： In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in integrated circuits in which the "bird's beak" problems associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on a silicon substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. Then, the silicon dioxide layer is, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride at the periphery of the openings is undercut.A layer of silicon is then deposited in the recesses covering the undercut portions of said silicon nitride layer. Then, the structure subjected to thermal oxidation whereby the silicon in and abutting the recesses is oxidized to form regions of recessed silicon dioxide substantially coplanar with the unrecessed portions of the silicon substrate. Because of the undercutting and the deposition of silicon in the recesses, the "bird's beak" effect is minimized.

公开(公告)号：US3933529A

公开(公告)日：1976-01-20

申请号：US487153

申请日：1974-07-10

申请人： Karl Goser

发明人： Karl Goser

IPC分类号： H01L27/092 ,  H01L21/225 ,  H01L21/8238 ,  H01L21/86 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L21/86 ,  H01L21/2255 ,  H01L27/12 ,  H01L29/78624 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/147 ,  Y10S148/151

摘要： A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which first and second gate electrodes are formed for the two transistors. A masking oxide layer is applied to the exposed surface regions of the gate insulating layer and the gate electrodes. An opening is etched into the masking layer and gate insulator layer lying adjacent each gate electrode. Charge carriers of first and second types are diffused through the respective openings into the region of the semiconductor layer lying below to dope the same. This doping extends partially into the semiconductor region lying beneath a portion of the respective gate electrodes. All parts of the gate insulator layer except those parts lying beneath the gate electrodes are removed. Charge carriers of the second and first type are diffused into the semiconductor layer on opposite sides of the first and second gate electrodes, respectively, while leaving a portion of the first and second doped regions unchanged beneath the first and second gate electrodes. The doped regions of the semiconductor layer on opposite sides of the first and second gate electrodes provide the source and drain regions of the first and second field effect transistors, respectively.

摘要翻译： 一种制造具有非常短的通道长度的一对互补场效应晶体管的方法。 轻掺杂半导体层沉积在电绝缘衬底上。 施加栅极绝缘体层，在两个晶体管上形成有第一和第二栅电极。 将掩模氧化物层施加到栅极绝缘层和栅电极的暴露的表面区域。 将掩模层和位于每个栅电极附近的栅极绝缘体层蚀刻开口。 第一和第二类型的电荷载体通过相应的开口扩散到位于下面的半导体层的区域以进​​行掺杂。 这种掺杂部分地延伸到位于相应栅电极的一部分下方的半导体区域中。 除去位于栅极下方的栅极绝缘体层的所有部分被去除。 第二和第一类型的电荷载体分别扩散到第一和第二栅电极的相对侧上的半导体层中，同时使第一和第二掺杂区域的一部分在第一和第二栅电极之下保持不变。 第一和第二栅电极的相对侧上的半导体层的掺杂区域分别提供第一和第二场效应晶体管的源区和漏区。

公开(公告)号：US3918997A

公开(公告)日：1975-11-11

申请号：US53050774

申请日：1974-12-06

申请人： BELL TELEPHONE LABOR INC

发明人： MOHSEN AMR MOHAMED ,  SEQUIN CARLO HEINRICH

IPC分类号： H01L21/00 ,  H01L21/339 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/768 ,  H01L21/263

CPC分类号： H01L29/76866 ,  H01L21/00 ,  H01L21/823406 ,  H01L29/1062 ,  H01L29/66954 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/122 ,  Y10S148/145 ,  Y10S438/981

摘要： A method for making charge coupled devices of the type which are addressable by a single clock phase. Photoresist masks are offset with respect to stepped oxide patterns in order to produce by ion implantation self-aligned surface regions which are needed for potential asymmetry. Such surface regions can thereby be made smaller than the minimum mask feature. The oxide pattern in the final device may be formed by using silicon nitride to mask against oxide growth in selected areas. A single layer of metal may then be formed over the oxide to establish a uniphase charge coupled device with a cell length which is just twice the size of the minimum mask feature.

摘要翻译： 一种用于制造可由单个时钟相位寻址的类型的电荷耦合器件的方法。 光刻胶掩模相对于阶梯状氧化物图案偏移，以便通过离子注入自对准表面区域产生电势不对称所需的表面区域。 因此，这样的表面区域可以被制成小于最小掩模特征。 最终器件中的氧化物图案可以通过使用氮化硅来掩蔽选择区域中的氧化物生长来形成。 然后可以在氧化物上形成单层金属，以建立单相电荷耦合器件，其单元长度仅为最小掩模特征尺寸的两倍。

公开(公告)号：US3897625A

公开(公告)日：1975-08-05

申请号：US45558974

申请日：1974-03-28

申请人： SIEMENS AG

发明人： TIHANYI JENO ,  SCHLOETTERER HEINRICH

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/322 ,  H01L21/331 ,  H01L21/86 ,  H01L29/73 ,  H01L29/786 ,  B01J17/00

CPC分类号： H01L21/2255 ,  H01L21/86 ,  H01L29/78624 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/15 ,  Y10S257/913

摘要： Method of making a field effect transistor having a short channel length which includes forming a protective covering layer on a silicon layer medium doped with an impurity that can be gettered, removing portions of the protective layer, forming a gettering layer on the exposed silicon surface where the portions of the protective covering has been removed, etching spaced areas of the getter layer and a portion of the protective covering adjacent one of the etched getter areas to provide source and drain diffusion windows, diffusing impurities of the opposite impurity type to the doping of the silicon layer through the windows to provide source and drain regions in the silicon layer separated by a channel region formed in its length in part by a medium doped region and in part by a low doped region, removing the protective covering from above the medium doped region, forming an insulating layer over the entire area, forming windows in the insulating layer above portions of the insulating layer above the source and drain regions, forming electrodes on the source and drain regions respectively and forming a gate electrode on the insulating layer above the highly doped channel region.

摘要翻译： 制造具有短沟道长度的场效应晶体管的方法，其包括在掺杂有杂质的硅层介质上形成保护覆盖层，所述杂质可以被吸收，去除保护层的部分，在暴露的硅表面上形成吸杂层， 已经去除了保护覆盖物的部分，蚀刻吸气剂层的间隔区域和与蚀刻的吸气剂区域相邻的保护覆盖物的一部分，以提供源极和漏极扩散窗口，将相反杂质类型的杂质扩散到 通过窗口提供硅层，以在硅层中提供源极和漏极区域，该沟道区域由其长度部分地由介质掺杂区域形成的沟道区域部分地由部分由低掺杂区域形成，从介质掺杂区域上方去除保护覆盖层 区域，在整个区域上形成绝缘层，在绝缘层的上方形成绝缘层上的窗口 g层，分别在源区和漏区上形成电极，并在高掺杂沟道区上方的绝缘层上形成栅电极。

公开(公告)号：US3886004A

公开(公告)日：1975-05-27

申请号：US33637573

申请日：1973-02-27

申请人： FERRANTI LTD

发明人： BRUCHEZ JEFFREY ALAN

IPC分类号： H01L21/00 ,  H01L21/316 ,  H01L21/762 ,  H01L7/36 ,  H01L27/04

CPC分类号： H01L21/76202 ,  H01L21/00 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  Y10S148/037 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/116 ,  Y10S148/118 ,  Y10S148/173 ,  Y10S438/911 ,  Y10S438/981

摘要： A silicon oxide layer is formed on a phosphorus doped surface region of a silicon semiconductor body by steam treatment, there being an enhanced growth rate of the silicon oxide on the phosphorus doped region enabling, for example, the provision of a low temperature steam treatment, and/or the production, possibly within an aperture in an already provided silicon oxide layer less than 3000A thick, of a thin silicon oxide layer, so that impurity concentration gradients within the semiconductor body are not caused to change by a significant extent and the surface concentration of phosphorus within the region is not significantly depleted.

摘要翻译： 通过蒸汽处理在硅半导体主体的磷掺杂表面区域上形成硅氧化物层，在磷掺杂区域上氧化硅的生长速度增加，能够提供例如低温蒸汽处理， 和/或可能在已经提供的小于3000厚的氧化硅层的氧化硅层的孔内生产薄氧化硅层，使得半导体本体内的杂质浓度梯度不会发生显着变化，并且表面 该区域内磷的浓度没有明显耗尽。

公开(公告)号：US3886000A

公开(公告)日：1975-05-27

申请号：US41309573

申请日：1973-11-05

申请人： IBM

发明人： BRATTER ROBERT L ,  GAIND ARUN K

IPC分类号： H01L21/76 ,  H01L21/31 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73 ,  H01L7/36 ,  H01L27/12

CPC分类号： H01L21/0214 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/76205 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/117

摘要： A dielectric isolation barrier is formed in a silicon substrate by oxidizing openings formed in an epitaxial layer on the substrate and a layer of silicon oxynitride (SiOxNy), which is on the surface of the epitaxial layer of the substrate. During this oxidation of the openings, the layer of silicon oxynitride is thermally oxidized to form an electrically insulating layer of silicon dioxide on the surface of the epitaxial layer and homogeneous with the silicon dioxide of the dielectric isolation barrier. The index of refraction of the layer of silicon oxynitride is selected in accordance with its thickness to produce a desired thickness of the layer of silicon dioxide after completion of oxidation of the openings in which the dielectric isolation barrier is formed. the index of refraction of silicon oxynitride is preferably between 1.55 and 1.70.

摘要翻译： 在硅衬底中通过氧化在衬底上的外延层中形成的开口和位于衬底的外延层的表面上的氧氮化硅层（SiO x N y）形成绝缘隔离屏障。 在这种开口氧化期间，氧氮化硅层被热氧化，以在外延层的表面上形成二氧化硅的电绝缘层，并与介电隔离屏障的二氧化硅均匀。 氧氮化硅层的折射率根据其厚度来选择，以在其中形成介电隔离屏障的开口的氧化完成之后产生所需的二氧化硅层厚度。 氮氧化硅的折射率优选在1.55和1.70之间。

公开(公告)号：US3880676A

公开(公告)日：1975-04-29

申请号：US41054873

申请日：1973-10-29

申请人： RCA CORP

发明人： DOUGLAS EDWARD CURTIS ,  WU CHUNG PAO ,  MUELLER CHARLES WILLIAM

IPC分类号： H01L29/73 ,  H01L21/00 ,  H01L21/265 ,  H01L21/331 ,  H01L7/54

CPC分类号： H01L21/00 ,  Y10S148/003 ,  Y10S148/015 ,  Y10S148/043 ,  Y10S148/113 ,  Y10S148/114 ,  Y10S148/145

摘要： In a method of making a transistor by ion implantation, wherein an emitter region is ion implanted through a window in a layer of silicon dioxide, a capping layer of silicon nitride is deposited over the emitter region before annealing the transistor, whereby out diffusion and evaporation of the emitter dopant atoms are prevented.

摘要翻译： 在通过离子注入制造晶体管的方法中，其中通过二氧化硅层中的窗口离子注入发射极区域，在退火晶体管之前，在发射极区域上沉积氮化硅覆盖层，从而使扩散和蒸发 的发射极掺杂剂原子。

公开(公告)号：USRE28386E

公开(公告)日：1975-04-08

申请号：US31774372

申请日：1972-12-22

IPC分类号： H01J29/45 ,  H01L21/00 ,  H01L23/29 ,  H01L27/00

CPC分类号： H01L23/291 ,  H01J9/233 ,  H01J29/455 ,  H01L21/00 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/049 ,  Y10S148/053 ,  Y10S148/118 ,  H01L2924/00

摘要： 1. IN A PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE, COMPRISING THE STEPS OF: PROVIDING A SUBSTRATE HAVING A NUMNER OF OPERATING SEMICONDUCTOR REGIONS FORMING AT LEAST ONE ACTIVE SEMICONDUCTOR ELEMENT, AT LEAST ONE OF SAID REGIONS BEING CONTIGUOUS WITH A GIVEN SURFACE OF SAID SUBSTRATE; FROMING A LAYER OF INSULATING MATERIAL ON SAID GIVEN SURFACE OVERLYING AT LEAST A PART OF SAID AT ONE REGION, SAID DEVICE INCLUDING AT LEAST ONE DELETERIOUS METAL INGREDIENT; EXPOSING SAID LAYER TO AN ATMOSPHERE COMPRISING A HYDROGEN HALIDE; AMD HEATING SAID SUBSTRATE TO A GIVEN TEMPERATURE SUFFICIENT TO CONVERT SAID METAL TO THE METAL HALIDE AND TO VOLATILIZE THE HALIDE AT THE EXPOSED SURFACE OF SAID INSULATING LAYER, THEREBY ESTABLISHING A GRADIENT FOR OUT-DIFFUSION OF SAID METAL FROM SAID DEVICE TOWARD SAID EXPOSED SURFACE, THE IMPROVEMENT WHEREIN SAID ATMOSPHERE IS MAINTAINED SUBSTANTIALLY FREE OF WATER VAPOR.