公开(公告)号：US20240088015A1

公开(公告)日：2024-03-14

申请号：US18462049

申请日：2023-09-06

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeewoong KIM ,  Hojun KIM ,  Sungmoon LEE ,  Seungmin CHA

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/58

CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L23/585

摘要： An integrated circuit device comprising: a dielectric layer; a first power delivery network layer on a first surface of the dielectric layer; a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface is opposite to the first surface in a vertical direction; and a via capacitor between the first surface and the second surface of the dielectric layer, wherein the via capacitor includes a first via electrode structure and a second via electrode structure that are spaced apart from each other in one of a first horizontal direction and a second horizontal direction that intersects with the first horizontal direction, and a first end portion and a second end portion that is opposite to the first end portion of the via capacitor are electrically connected to the first power delivery network layer and the second power delivery network layer, respectively.

公开(公告)号：US20240047513A1

公开(公告)日：2024-02-08

申请号：US17882794

申请日：2022-08-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Hui SU ,  Hsin-Li CHENG ,  Felix YingKit TSUI ,  Yu-Chi CHANG

IPC分类号： H01L49/02 ,  H01L21/764 ,  H01L23/522 ,  H01L23/58 ,  H01L21/768

CPC分类号： H01L28/91 ,  H01L21/764 ,  H01L23/5223 ,  H01L23/585 ,  H01L28/75 ,  H01L21/76816

摘要： Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure comprises a substrate comprising a first trench, wherein the first trench extends into a front side surface of the substrate, a first trench capacitor comprising a plurality of first capacitor electrode layers and a plurality of first capacitor dielectric layers disposed in alternating manner within the first trench and over the front side surface of the substrate, wherein a first air gap is enclosed by the plurality of first capacitor electrode layers and the plurality of first capacitor dielectric layers within the first trench, an interconnect structure disposed over the first trench capacitor, wherein one or more first capacitor electrode layers of the plurality of first capacitor electrode layers are in electrical connection with a first conductive feature in a dielectric layer of the interconnect structure, and a first seal ring structure disposed in the interconnect structure and encircling an interior portion of the substrate, wherein at least a portion of the first seal ring structure is in contact with the first conductive feature

公开(公告)号：US20240038689A1

公开(公告)日：2024-02-01

申请号：US18485709

申请日：2023-10-12

申请人： Apple Inc.

发明人： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L23/544

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L23/564 ,  H01L23/585 ,  H01L23/544 ,  H01L2223/5446

摘要： Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20240038688A1

公开(公告)日：2024-02-01

申请号：US18485291

申请日：2023-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zi-Jheng LIU ,  Jo-Lin LAN ,  Yu-Hsiang HU ,  Hung-Jui KUO

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/58 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683

CPC分类号： H01L23/562 ,  H01L23/5389 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/544 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/78 ,  H01L23/3128 ,  H01L21/6835 ,  H01L23/5386 ,  H01L23/564 ,  H01L21/4853 ,  H01L2223/5446 ,  H01L2224/19 ,  H01L21/561

摘要： A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.

公开(公告)号：US20240038674A1

公开(公告)日：2024-02-01

申请号：US18481961

申请日：2023-10-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Chi Chu ,  Hung-Jui Kuo ,  Jhih-Yu Wang ,  Yu-Hsiang Hu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L21/4853 ,  H01L2224/214 ,  H01L2221/68372

摘要： A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

公开(公告)号：US20240030160A1

公开(公告)日：2024-01-25

申请号：US18479230

申请日：2023-10-02

申请人： GlobalFoundries U.S. Inc.

发明人： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC分类号： H01L23/00 ,  G06F30/392 ,  H01L23/66 ,  H03H1/00 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L23/564 ,  G06F30/392 ,  H01L23/66 ,  H03H1/0007 ,  H01L23/585

摘要： Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US20240030158A1

公开(公告)日：2024-01-25

申请号：US18355556

申请日：2023-07-20

申请人： Apple Inc.

发明人： Szu-Ying Ho ,  Jeng-Wen P Chen ,  Hsiu-Ping Wei

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L21/78

CPC分类号： H01L23/562 ,  H01L23/585 ,  H01L21/78

摘要： Systems and methods are provided for reducing damage caused by defects from a scribe lane of an integrated circuit, which may arise during or after a silicon wafer is singulated into separate integrated circuits. An integrated circuit may include an active area and a scribe lane. The scribe lane may include a crack energy release zone or a crack take-off zone, or both. The crack energy release zone may dissipate fracture energy in an event that a crack were to form in the scribe lane. The crack take-off zone may, in the event that the crack were to form in the scribe lane, guide the crack out of a surface of the integrated circuit in the crack take-off zone.

公开(公告)号：US20240021544A1

公开(公告)日：2024-01-18

申请号：US18358343

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chia Hu ,  Chun-Chiang Kuo ,  Sen-Bor Jan ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC分类号： H01L23/58 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/585 ,  H01L23/5226 ,  H01L23/53295 ,  H01L29/0649 ,  H01L24/09 ,  H01L24/83 ,  H01L24/03 ,  H01L24/33 ,  H01L25/50 ,  H01L24/80 ,  H01L25/0657 ,  H01L23/562 ,  H01L2225/06568 ,  H01L2225/06565 ,  H01L2225/06593 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2224/94

摘要： A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

公开(公告)号：US11869859B2

公开(公告)日：2024-01-09

申请号：US17460180

申请日：2021-08-28

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Jen-Yuan Chang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L24/06 ,  H01L24/08 ,  H01L24/32 ,  H01L24/83 ,  H01L23/585 ,  H01L24/05 ,  H01L24/29 ,  H01L2224/05647 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/2919 ,  H01L2224/29186 ,  H01L2224/32145 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/8385 ,  H01L2224/83203 ,  H01L2224/83896

摘要： A die stack includes: a first die including a first semiconductor substrate; a second die including a second semiconductor substrate; a bonding dielectric structure including a bonding polymer and that bonds the first die and the second die; a bonding interconnect structure that extends through the bonding dielectric structure to bond and electrically connect the first die and the second die; and a bonding dummy pattern that extends through the bonding dielectric structure to bond the first die and the second die. The bonding dummy pattern is electrically conductive and is electrically floated.

公开(公告)号：US20240006356A1

公开(公告)日：2024-01-04

申请号：US18181731

申请日：2023-03-10

申请人： Samsung Electronics Co., Ltd.

发明人： INHYO HWANG ,  YOUNG LYONG KIM ,  HYUNSOO CHUNG

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L23/58 ,  H10B80/00 ,  H01L21/78

CPC分类号： H01L24/06 ,  H01L22/32 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/08 ,  H01L2924/35121 ,  H01L21/78 ,  H01L22/12 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B80/00

摘要： A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads. Ones of the first metal pads may be in contact with respective ones of the second metal pads on the device region, and ones of the first dummy pads may be in contact with respective ones of the second dummy pads on the edge region.