公开(公告)号：US20210028092A1

公开(公告)日：2021-01-28

申请号：US17071137

申请日：2020-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG LYONG KIM ,  SEUNGDUK BAEK

IPC: H01L23/488 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

公开(公告)号：US20240040805A1

公开(公告)日：2024-02-01

申请号：US18122285

申请日：2023-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  YOUNG LYONG KIM ,  Inhyo HWANG

IPC: H10B80/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H10B80/00 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package may include a substrate, a chip structure mounted on the substrate, and a first dummy structure attached to the chip structure. The chip structure may include a first semiconductor chip, a second dummy structure disposed at a side of the first semiconductor chip, and a mold layer enclosing the first semiconductor chip and the second dummy structure. A bottom surface of the first semiconductor chip, a bottom surface of the second dummy structure, and a bottom surface of the mold layer may be coplanar with each other.

公开(公告)号：US20230023883A1

公开(公告)日：2023-01-26

申请号：US17568361

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNSOO CHUNG ,  YOUNG LYONG KIM ,  INHYO HWANG

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

公开(公告)号：US20220199561A1

公开(公告)日：2022-06-23

申请号：US17366145

申请日：2021-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG LYONG KIM

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package including a first die, through electrodes penetrating the first die, a first pad on a top surface of the first die and coupled to a through electrode, a second die on the first die, a second pad on a bottom surface of the second die, a first connection terminal connecting the first pad to the second pad, and an insulating layer that fills a region between the first die and the second die and encloses the first connection terminal. The first connection terminal includes an intermetallic compound made of solder material and metallic material of the first and second pads. A concentration of the metallic material in the first connection terminal is substantially constant regardless of a distance from the first pad or the second pad.

公开(公告)号：US20240421000A1

公开(公告)日：2024-12-19

申请号：US18392481

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  YOUNG LYONG KIM ,  SUNGWOO PARK

IPC: H01L21/78 ,  H01L23/00

Abstract: A semiconductor die includes: a first surface; a second surface opposite to the first surface; and a first side surface, a second side surface, a third side surface, and a fourth side surface between the first surface and the second surface, in which the first side surface faces the third side surface, and a roughness of the second side surface varies according to area, and a roughness of at least a portion of the second side surface is greater than that of the first side surface.

公开(公告)号：US20220415809A1

公开(公告)日：2022-12-29

申请号：US17539963

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG LYONG KIM ,  HYUNSOO CHUNG ,  INHYO HWANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

公开(公告)号：US20220013487A1

公开(公告)日：2022-01-13

申请号：US17163401

申请日：2021-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG LYONG KIM

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31

Abstract: Disclosed is a semiconductor package comprising a package substrate, a substrate on the package substrate, a first semiconductor chip mounted on the substrate, and a stiffener structure on the package substrate and having a hole. The stiffener structure is laterally spaced apart from the substrate. The hole penetrates a top surface of the stiffener structure and a bottom surface of the stiffener structure. When viewed in plan, the hole overlaps a corner region of the package substrate.

公开(公告)号：US20190244878A1

公开(公告)日：2019-08-08

申请号：US16124225

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG LYONG KIM ,  SEUNGDUK BAEK

IPC: H01L23/488 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/488 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

公开(公告)号：US20250096214A1

公开(公告)日：2025-03-20

申请号：US18626691

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  YOUNG LYONG KIM ,  CHI WOO LEE

IPC: H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H10B80/00

Abstract: An embodiment provides a semiconductor package including: a redistribution structure; an interconnection structure on the redistribution structure; a memory stacking structure disposed on the redistribution structure and including a buffer die and core dies stacked on the buffer die; a semiconductor die disposed on the buffer die and on the interconnection structure; and an optical engine disposed on the interconnection structure.

公开(公告)号：US20240429202A1

公开(公告)日：2024-12-26

申请号：US18417004

申请日：2024-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO SHIN ,  YOUNG LYONG KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes: a first substrate including lower bonding pads; at least one semiconductor chip disposed on the first substrate; bumps disposed on a first surface of the first substrate; and a mold layer disposed on the first substrate and covering the at least one semiconductor chip, wherein the bumps include: a pillar portion bonded to the first surface of the first substrate; a solder portion bonded to a first surface of the pillar portion; and a metal layer including a material including high-melting-point metal atoms, wherein the metal layer covers a first surface of the solder portion, wherein the solder portion includes the high-melting-point metal atoms.