公开(公告)号：US20200312826A1

公开(公告)日：2020-10-01

申请号：US16583051

申请日：2019-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  CHULWOO KIM ,  HYO-CHANG RYU ,  YUN SEOK CHOI

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/528 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

公开(公告)号：US20240421000A1

公开(公告)日：2024-12-19

申请号：US18392481

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  YOUNG LYONG KIM ,  SUNGWOO PARK

IPC: H01L21/78 ,  H01L23/00

Abstract: A semiconductor die includes: a first surface; a second surface opposite to the first surface; and a first side surface, a second side surface, a third side surface, and a fourth side surface between the first surface and the second surface, in which the first side surface faces the third side surface, and a roughness of the second side surface varies according to area, and a roughness of at least a portion of the second side surface is greater than that of the first side surface.

公开(公告)号：US20230335540A1

公开(公告)日：2023-10-19

申请号：US18338372

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  CHULWOO KIM ,  HYO-CHANG RYU ,  YUN SEOK CHOI

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L23/48 ,  H01L21/683 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L25/16 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/95001

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.

公开(公告)号：US20230326862A1

公开(公告)日：2023-10-12

申请号：US18326325

申请日：2023-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YANGGYOO JUNG ,  JINHYUN KANG ,  SUNGEUN KIM ,  SANGMIN YONG ,  SEUNGKWAN RYU

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L23/49816 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2924/1517 ,  H01L2224/73204 ,  H01L24/73

Abstract: A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer includes a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.

公开(公告)号：US20220189916A1

公开(公告)日：2022-06-16

申请号：US17398406

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  Sungeun KIM ,  SANGMIN YONG ,  HAE-JUNG YU

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/64

Abstract: A semiconductor package comprising a package substrate that extends in a first direction and a second direction perpendicular to the first direction, a plurality of logic dies and a memory stack structure on the package substrate, and an interposer substrate mounted in the package substrate. The memory stack structure vertically overlaps the interposer substrate. Each of the logic dies includes a first part that is horizontally offset from the interposer substrate and a second part that vertically overlaps the interposer substrate. The interposer substrate includes an interlayer dielectric layer and a plurality of wiring lines in the interlayer dielectric layer. The memory stack structure is electrically connected to at least one of the logic dies through the wiring lines of the interposer substrate.

公开(公告)号：US20210366884A1

公开(公告)日：2021-11-25

申请号：US17396308

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： YANGGYOO JUNG ,  CHULWOO KIM ,  HYO-CHANG RYU ,  YUN SEOK CHOI

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/48 ,  H01L23/367 ,  H01L23/00 ,  H01L21/78 ,  H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538

Abstract: A semiconductor package may include a package substrate, a first interposer substrate mounted on the package substrate, and a first semiconductor chip disposed on the first interposer substrate. The first interposer substrate may include a first base layer, a second base layer disposed on the first base layer, circuit patterns provided in each of the first base layer and the second base layer, and an integrated device embedded in the first base layer and connected to at least one of the circuit patterns. A top surface of the first base layer may contact a bottom surface of the second base layer.