公开(公告)号：US20240038688A1

公开(公告)日：2024-02-01

申请号：US18485291

申请日：2023-10-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zi-Jheng LIU ,  Jo-Lin LAN ,  Yu-Hsiang HU ,  Hung-Jui KUO

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/58 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683

CPC分类号： H01L23/562 ,  H01L23/5389 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/585 ,  H01L23/544 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/78 ,  H01L23/3128 ,  H01L21/6835 ,  H01L23/5386 ,  H01L23/564 ,  H01L21/4853 ,  H01L2223/5446 ,  H01L2224/19 ,  H01L21/561

摘要： A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.

公开(公告)号：US20210296262A1

公开(公告)日：2021-09-23

申请号：US17340036

申请日：2021-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zi-Jheng LIU ,  Jo-Lin LAN ,  Yu-Hsiang HU ,  Hung-Jui KUO

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/58 ,  H01L23/544 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683

摘要： A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.

公开(公告)号：US20190172796A1

公开(公告)日：2019-06-06

申请号：US16272935

申请日：2019-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zi-Jheng LIU ,  Jo-Lin LAN ,  Yu-Hsiang HU ,  Hung-Jui KUO

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/58 ,  H01L23/544 ,  H01L21/78 ,  H01L23/538

摘要： A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.

公开(公告)号：US20220269184A1

公开(公告)日：2022-08-25

申请号：US17185827

申请日：2021-02-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Cheng LIN ,  Chien Rhone WANG ,  Kewei ZUO ,  Ming-Tan LEE ,  Zi-Jheng LIU

IPC分类号： G03F7/20 ,  G06N20/00 ,  G06K9/62

摘要： The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and machine learning are used to train a classification that correlates the overlay error source factors with overlay metrology categories. The overlay error source factors include tool signals. The trained classification includes a base classification and a Meta classification.

公开(公告)号：US20170317034A1

公开(公告)日：2017-11-02

申请号：US15289173

申请日：2016-10-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Zi-Jheng LIU ,  Jo-Lin LAN ,  Yu-Hsiang HU ,  Hung-Jui KUO

IPC分类号： H01L23/00 ,  H01L23/58 ,  H01L23/544 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/564 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244

摘要： A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip region, and a scribe region surroundingly defined around the seal ring region, the semiconductor structure including: a semiconductor chip in the chip region; and a molding compound disposed around the semiconductor chip and distributed in the chip region, the seal ring region and the scribe region; forming an insulating film over the chip region of the semiconductor structure and the seal ring region of the semiconductor structure; forming a seal ring over the seal ring region of the semiconductor structure and laterally adjacent to the insulating film, in which the seal ring has an exposed lateral surface facing away from the insulating film; and forming a protective layer that defines a substantially smooth and inclined lateral surface over the exposed lateral surface of the seal ring.