公开(公告)号：US11862481B2

公开(公告)日：2024-01-02

申请号：US17460806

申请日：2021-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Chi Nung Ni ,  Long Huang ,  SivaChandra Jangam

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/32059 ,  H01L2224/32137 ,  H01L2924/183

Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

公开(公告)号：US20250112192A1

公开(公告)日：2025-04-03

申请号：US18656367

申请日：2024-05-06

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  SivaChandra Jangam ,  Kunzhong Hu

IPC: H01L23/00 ,  G02B6/43 ,  H01L23/15 ,  H01L23/48 ,  H01L23/498 ,  H01L25/16

Abstract: A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. First-level dies and second-level dies can be bonded to the mid-layer interposer with ultra fine micro bumps. Dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

公开(公告)号：US20240105626A1

公开(公告)日：2024-03-28

申请号：US18296587

申请日：2023-04-06

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  SivaChandra Jangam ,  Zhitao Cao

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49894 ,  H01L23/5383 ,  H01L28/40

Abstract: Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.

公开(公告)号：US20220293433A1

公开(公告)日：2022-09-15

申请号：US17460806

申请日：2021-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Chi Nung Ni ,  Long Huang ,  SivaChandra Jangam

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/00

Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

公开(公告)号：US20240103238A1

公开(公告)日：2024-03-28

申请号：US18458892

申请日：2023-08-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  SivaChandra Jangam

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/4279 ,  G02B6/4283 ,  G02B6/4293

Abstract: A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. Second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds. Dies within the first and/or second package levels may optionally be connected with one or more optical interconnect paths.

公开(公告)号：US20230040308A1

公开(公告)日：2023-02-09

申请号：US17397834

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US12261132B2

公开(公告)日：2025-03-25

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20240105699A1

公开(公告)日：2024-03-28

申请号：US17934409

申请日：2022-09-22

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  SivaChandra Jangam

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80379 ,  H01L2224/80444 ,  H01L2224/80447

Abstract: A system in package structure and method of fabrication using wafer reconstitution are described. In an embodiment a 3D system includes a mid-layer interposer a first package level underneath the mid-layer interposer and a second package level over the mid-layer interposer. Second package level components can be bonded to the mid-layer interposer with metal-metal bonds and optionally dielectric-dielectric bonds, while the first package level components can be bonded to the mid-layer interposer with dielectric-dielectric and optionally metal-metal bonds.

公开(公告)号：US20240096648A1

公开(公告)日：2024-03-21

申请号：US18509801

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Chi Nung Ni ,  Long Huang ,  SivaChandra Jangam

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/56 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/32059 ,  H01L2224/32137 ,  H01L2924/183

Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.

公开(公告)号：US20240038689A1

公开(公告)日：2024-02-01

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/564 ,  H01L23/585 ,  H01L23/544 ,  H01L2223/5446

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.