知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

457 条记录 (耗时 0.021 秒)

    Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs
    11.
    发明申请
    Systems and Methods Involving Multi-Bank, Dual- or Multi-Pipe SRAMs 审中-公开
    涉及多行，双管或多管SRAM的系统和方法

    公开(公告)号：US20160189766A1

    公开(公告)日：2016-06-30

    申请号：US14951160

    申请日：2015-11-24

    申请人： GSI Technology, Inc.

    发明人： Robert Haig ,  Patrick CHUANG ,  Chih TSENG ,  Mu-Hsiang HUANG

    IPC分类号： G11C11/406 ,  G11C7/10

    CPC分类号： G11C11/40615 ,  G06F13/1615 ,  G11C7/1039 ,  G11C7/1072 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

    摘要： Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

    摘要翻译： 公开了用于增加静态随机存取存储器（SRAM）的性能的系统和方法。 这里的各种系统例如可以包括或涉及双管或多管多段SRAM，例如Quad-B2 SRAM。 在一个说明性实现中，提供了一种SRAM存储器件，其包括存储器阵列，该存储器阵列包括多个SRAM组以及与每个SRAM组相关联的独立和不同的管对，其中每对管可以提供对其相关联的SRAM的独立访问 银行。

    LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE
    12.
    发明申请
    LOW POWER DOUBLE PUMPED MULTI-PORT REGISTER FILE ARCHITECTURE 有权
    低功耗双泵浦多端口注册文件架构

    公开(公告)号：US20160055889A1

    公开(公告)日：2016-02-25

    申请号：US14467376

    申请日：2014-08-25

    申请人： Apple Inc.

    发明人： Ajay Kumar Bhatia ,  Aravind Kandala

    IPC分类号： G11C7/22 ,  G11C7/10

    CPC分类号： G11C7/222 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/419 ,  G11C2207/2254 ,  G11C2207/229

    摘要： Embodiments that may allow for selectively tuning a delay of individual write paths within a memory are disclosed. The memory may comprise a memory array, a first data latch, a second data latch, and circuitry. The first and second data latches may be configured to each sample a respective data value, responsive to detecting a first edge of a first clock signal. The circuitry may be configured to detect the first edge of the first clock signal, and select an output of the first data latch responsive to detecting the first edge of the first clock signal. The circuitry may detect a subsequent opposite edge of the first clock signal, and select an output of the second data latch responsive to sampling the opposite edge of the first clock signal.

    摘要翻译： 公开了可以允许选择性地调整存储器内的各个写入路径的延迟的实施例。 存储器可以包括存储器阵列，第一数据锁存器，第二数据锁存器和电路。 响应于检测到第一时钟信号的第一边缘，第一和第二数据锁存器可以被配置为对各自的数据值进行采样。 电路可以被配置为检测第一时钟信号的第一边缘，并且响应于检测到第一时钟信号的第一边缘而选择第一数据锁存器的输出。 电路可以检测第一时钟信号的后续相对边缘，并且响应于对第一时钟信号的相对边缘采样来选择第二数据锁存器的输出。

    Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
    15.
    发明授权
    Systems and methods involving multi-bank, dual- or multi-pipe SRAMs 有权
    涉及多管，双管或多管SRAM的系统和方法

    公开(公告)号：US09196324B2

    公开(公告)日：2015-11-24

    申请号：US14170497

    申请日：2014-01-31

    申请人： GSI Technology, Inc.

    发明人： Robert Haig ,  Patrick Chuang ,  Chih Tseng ,  Mu-Hsiang Huang

    IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C11/419 ,  G06F13/16

    CPC分类号： G11C11/40615 ,  G06F13/1615 ,  G11C7/1039 ,  G11C7/1072 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

    摘要： Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

    摘要翻译： 公开了用于增加静态随机存取存储器（SRAM）的性能的系统和方法。 这里的各种系统例如可以包括或涉及双管或多管多段SRAM，例如Quad-B2 SRAM。 在一个说明性实现中，提供了一种SRAM存储器件，其包括存储器阵列，该存储器阵列包括多个SRAM组以及与每个SRAM组相关联的独立和不同的管对，其中每对管可以提供对其相关联的SRAM的独立访问 银行。

    Semiconductor memory device with sequentially generated delay signals
    16.
    发明授权
    Semiconductor memory device with sequentially generated delay signals 有权
    具有顺序产生的延迟信号的半导体存储器件

    公开(公告)号：US09190130B2

    公开(公告)日：2015-11-17

    申请号：US13717357

    申请日：2012-12-17

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4097

    CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/227 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/229

    摘要： A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

    摘要翻译： 半导体存储器件包括：第一信号生成单元，被配置为响应于第一列控制信号顺次生成第一和第二延迟信号，所述第一和第二延迟信号具有反射的延迟时间和从多个延迟中选择的相乘的延迟时间 分别通过数据输入/输出与单位存储区域的布置位置对应的时间，以及第二信号生成单元，被配置为产生与第一列控制信号相比延迟了所选择的延迟时间的第二列控制信号 响应于第一延迟信号确定第二列控制信号的激活时间点，并响应于第二延迟信号确定第二列控制信号的去激活时间点。

    SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY
    17.
    发明申请
    SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY 审中-公开
    并联读/写磁阻存储器的系统和方法

    公开(公告)号：US20150310904A1

    公开(公告)日：2015-10-29

    申请号：US14263632

    申请日：2014-04-28

    申请人： QUALCOMM Incorporated

    发明人： Taehyun KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Xiangyu DONG

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1653 ,  G11C7/1039 ,  G11C7/1042 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

    摘要： In a memory having a first memory cell array, a second memory cell array, an address is received on an address port. Based on the address, an internal address is transmitted, and it is latched and held for a first interval as a first array address. The first memory cell array is accessed over the first interval, based on the first array address. Another address is received at the address port, during the first interval, and another internal address is transmitted, and latched and held for a second interval that overlaps the first interval, as a second array address. The second memory cell array is accessed during the second interval, based on the second array address.

    摘要翻译： 在具有第一存储单元阵列的存储器中，第二存储单元阵列在地址端口上接收地址。 基于该地址，发送内部地址，并将其锁存并保持第一间隔作为第一阵列地址。 基于第一个阵列地址，第一个存储单元阵列在第一个时间间隔内被访问。 在第一间隔期间在地址端口处接收另一地址，并且发送另一内部地址，并将其锁存并保持与第一间隔重叠的第二间隔作为第二阵列地址。 基于第二阵列地址在第二间隔期间访问第二存储单元阵列。

    Concurrent memory bank access and refresh retirement
    19.
    发明授权
    Concurrent memory bank access and refresh retirement 有权
    并发记忆库访问和刷新退休

    公开(公告)号：US08151044B2

    公开(公告)日：2012-04-03

    申请号：US12635543

    申请日：2009-12-10

    申请人： Robert Proesbsting

    发明人： Robert Proesbsting

    IPC分类号： G06F12/00

    CPC分类号： G11C11/40618 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/104 ,  G11C2207/229 ,  H01L27/10891 ,  H01L27/10897

    摘要： A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

    摘要翻译： 动态随机存取存储器集成电路和方法包括内部刷新控制和被配置为接收具有优先于待处理刷新请求的优先级的读和写访问请求的阵列，其中刷新请求可排队并且在不需要阵列访问并且完成的时钟周期上退休 在一个时钟周期。 不需要板载高速缓存。 一种方法包括：当阵列中的一个阵列需要刷新时确定电路内的优先次序，优先考虑未决刷新请求的读取和写入访问请求，启动对阵列的访问的读取访问请求，而不确定数据是否可从数组外部获得 ，并且当该银行具有待处理的刷新请求并且不需要在该时钟周期上访问数组时，在一个时钟周期内退出一个等待刷新请求到银行。

    High speed DRAM architecture with uniform access latency
    20.
    发明授权
    High speed DRAM architecture with uniform access latency 失效
    具有均匀访问延迟的高速DRAM架构

    公开(公告)号：US08045413B2

    公开(公告)日：2011-10-25

    申请号：US12785051

    申请日：2010-05-21

    申请人： Paul Demone

    发明人： Paul Demone

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C11/408 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/405 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

    摘要翻译： 动态随机存取存储器（DRAM）执行读，写和刷新操作。 DRAM包括多个子阵列，每个子阵列具有多个存储器单元，每个存储单元与互补位线对和字线耦合。 DRAM还包括用于断言所选择的一条字线的字线使能装置和用于断言所选位线对之一的列选择装置。 提供了一种定时电路，用于响应于字线定时脉冲来控制字线使能装置，列选择装置以及读，写和刷新操作。 读取，写入和刷新操作在相同的时间内执行。