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    Semiconductor memory device using delays to control column signals for different memory regions
    1.
    发明授权
    Semiconductor memory device using delays to control column signals for different memory regions 有权
    半导体存储器件使用延迟来控制不同存储区域的列信号

    公开(公告)号：US09520167B2

    公开(公告)日：2016-12-13

    申请号：US14943639

    申请日：2015-11-17

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park

    IPC分类号： G11C7/22 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4097 ,  G11C7/06 ,  G11C8/10

    CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/227 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/229

    摘要： A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

    摘要翻译： 半导体存储器件包括：第一信号生成单元，被配置为响应于第一列控制信号顺次生成第一和第二延迟信号，所述第一和第二延迟信号具有反射的延迟时间和从多个延迟中选择的相乘的延迟时间 分别通过数据输入/输出与单位存储区域的布置位置对应的时间，以及第二信号生成单元，被配置为产生与第一列控制信号相比延迟了所选择的延迟时间的第二列控制信号 响应于第一延迟信号确定第二列控制信号的激活时间点，并响应于第二延迟信号确定第二列控制信号的去激活时间点。

    Memory and memory system
    2.
    发明授权
    Memory and memory system 有权
    内存和内存系统

    公开(公告)号：US09165614B2

    公开(公告)日：2015-10-20

    申请号：US14049878

    申请日：2013-10-09

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park ,  Kang-Seol Lee

    IPC分类号： G11C8/00 ,  G11C7/10 ,  G11C8/12 ,  G11C5/02

    CPC分类号： G11C7/10 ,  G11C5/025 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/12 ,  G11C29/1201 ,  G11C2207/107

    摘要： A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.

    摘要翻译： 存储器可以包括被配置为包括分别对应于第一至第N单元阵列的多个存储单元和一个或多个第一至第N数据输入/输出垫的第一至第N单元阵列，其中所述一个或多个第一至第N数据输入/ 输出焊盘被配置为向/从第一至第N单元阵列输入/输出数据。

    Integrated circuit chip
    3.
    发明授权
    Integrated circuit chip 有权

    公开(公告)号：US10748601B2

    公开(公告)日：2020-08-18

    申请号：US16127845

    申请日：2018-09-11

    申请人： SK hynix Inc.

    发明人： Ji-Hwan Kim ,  Heat-Bit Park

    IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C5/06 ,  G11C29/36 ,  G11C29/02 ,  G11C5/02 ,  G11C29/12

    摘要： An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.

    Semiconductor device having through-silicon via
    4.
    发明授权
    Semiconductor device having through-silicon via 有权
    具有通硅通孔的半导体器件

    公开(公告)号：US09263371B2

    公开(公告)日：2016-02-16

    申请号：US14303286

    申请日：2014-06-12

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park

    IPC分类号： G11C7/22 ,  H01L23/48 ,  H01L25/18

    CPC分类号： H01L23/481 ,  G11C5/063 ,  G11C7/22 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.

    摘要翻译： 半导体器件包括垂直穿过半导体器件的通孔; 电连接所述通孔和外部的金属垫; 数据输入块，用于响应写入命令将数据信号传送到金属焊盘; 通过电极存储块，适于存储通过金属焊盘传送的数据信号; 以及适于根据读取命令将存储在通过电极存储块中的数据信号输出到外部的数据输出块。

    Semiconductor memory device with sequentially generated delay signals
    5.
    发明授权
    Semiconductor memory device with sequentially generated delay signals 有权
    具有顺序产生的延迟信号的半导体存储器件

    公开(公告)号：US09190130B2

    公开(公告)日：2015-11-17

    申请号：US13717357

    申请日：2012-12-17

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4097

    CPC分类号： G11C7/22 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/12 ,  G11C7/227 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/229

    摘要： A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

    摘要翻译： 半导体存储器件包括：第一信号生成单元，被配置为响应于第一列控制信号顺次生成第一和第二延迟信号，所述第一和第二延迟信号具有反射的延迟时间和从多个延迟中选择的相乘的延迟时间 分别通过数据输入/输出与单位存储区域的布置位置对应的时间，以及第二信号生成单元，被配置为产生与第一列控制信号相比延迟了所选择的延迟时间的第二列控制信号 响应于第一延迟信号确定第二列控制信号的激活时间点，并响应于第二延迟信号确定第二列控制信号的去激活时间点。

    Integrated circuit
    7.
    发明授权
    Integrated circuit 有权

    公开(公告)号：US10991400B2

    公开(公告)日：2021-04-27

    申请号：US16221757

    申请日：2018-12-17

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park ,  Ji-Hwan Kim ,  Dong-Uk Lee

    IPC分类号： G11C7/10

    摘要： An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.