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18 条记录 (耗时 0.012 秒)

    Memory
    1.
    发明授权
    Memory 有权

    公开(公告)号：US11416425B2

    公开(公告)日：2022-08-16

    申请号：US16841466

    申请日：2020-04-06

    申请人： SK hynix Inc.

    发明人： Dong-Uk Lee

    IPC分类号： G06F13/16 ,  G06F3/06 ,  H01L25/18 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065 ,  H03M9/00

    摘要： A memory includes: a first data bus; a second data bus; and a plurality of bank groups. The bank groups output read data by alternately using the first data bus and the second data bus during read operations of the bank groups. One of the plurality of bank groups transfer read data to the first data bus during a read operation based on an odd-numbered read command. Further, one of the plurality of bank groups transfer transfer one of the plurality of bank groups read data to the second data bus during a read operation based on an even-numbered read command.

    Memory device with interleaved bank access
    2.
    发明授权
    Memory device with interleaved bank access 有权

    公开(公告)号：US10204665B2

    公开(公告)日：2019-02-12

    申请号：US15862241

    申请日：2018-01-04

    申请人： SK hynix Inc.

    发明人： Kyung-Whan Kim ,  Dong-Uk Lee

    IPC分类号： G11C7/10 ,  G06F13/40 ,  G11C7/22 ,  G11C8/18 ,  G06F13/42 ,  G06F13/16 ,  G11C8/12

    摘要： A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

    Memory device and memory system including the same
    4.
    发明授权
    Memory device and memory system including the same 有权
    存储器件和存储器系统包括相同的

    公开(公告)号：US09361961B2

    公开(公告)日：2016-06-07

    申请号：US14303230

    申请日：2014-06-12

    申请人： SK hynix Inc.

    发明人： Young-Ju Kim ,  Dong-Uk Lee

    IPC分类号： G11C8/12 ,  G11C11/40 ,  G11C8/18 ,  G11C11/408 ,  G11C11/406

    CPC分类号： G11C8/18 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4087

    摘要： A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

    摘要翻译： 存储装置可以包括多个存储体，适于接收多个行控制信号的行控制信号输入单元，适于接收多个列控制信号的列控制信号输入单元，适于选择的行控制单元 响应于行控制信号的存储体和行，以及控制所选行的行操作，以及响应于列控制信号选择存储体和列的列控制单元，并且控制列操作 为所选列。

    Integrated circuit
    5.
    发明授权
    Integrated circuit 有权

    公开(公告)号：US10991400B2

    公开(公告)日：2021-04-27

    申请号：US16221757

    申请日：2018-12-17

    申请人： SK hynix Inc.

    发明人： Heat-Bit Park ,  Ji-Hwan Kim ,  Dong-Uk Lee

    IPC分类号： G11C7/10

    摘要： An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.

    Semiconductor integrated circuit including master chip and slave chip that are stacked
    6.
    发明授权
    Semiconductor integrated circuit including master chip and slave chip that are stacked 有权

    公开(公告)号：US10424355B2

    公开(公告)日：2019-09-24

    申请号：US15678662

    申请日：2017-08-16

    申请人： SK hynix Inc.

    发明人： Dong-Uk Lee ,  Young-Ju Kim ,  Keun-Soo Song

    IPC分类号： G11C7/22 ,  G11C8/18 ,  G11C7/10 ,  G11C7/12

    摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

    SEMICONDUCTOR INTEGRATED CIRCUIT
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20160141014A1

    公开(公告)日：2016-05-19

    申请号：US15004060

    申请日：2016-01-22

    申请人： SK hynix Inc.

    发明人： Dong-Uk Lee ,  Young-Ju Kim ,  Keun-Soo Song

    IPC分类号： G11C7/22 ,  G11C7/12 ,  G11C7/10

    CPC分类号： G11C7/222 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1054 ,  G11C7/1081 ,  G11C7/12 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/107

    摘要： A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.

    摘要翻译： 一种半导体集成电路，包括垂直堆叠的第一半导体芯片和第二半导体芯片，其中，所述第一半导体芯片包括第一列数据驱动电路，其被配置为以基于以下的DDR（双倍数据速率）方案将内部数据传输到所述第二半导体芯片 内部选通信号和第一列选通信号驱动电路，被配置为基于内部选通信号产生与由第一列数据驱动电路发送到第二半导体芯片的第一列数据源同步的第一列选通信号， 并将第一列选通信号发送到第二半导体芯片。

    Stacked semiconductor device
    9.
    发明授权
    Stacked semiconductor device 有权

    公开(公告)号：US10074579B1

    公开(公告)日：2018-09-11

    申请号：US15709785

    申请日：2017-09-20

    申请人： SK hynix Inc.

    发明人： Ji-Hwan Kim ,  Dong-Uk Lee

    IPC分类号： H01L21/66 ,  H01L25/065 ,  G01R31/28 ,  G01R31/02

    摘要： A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die, and suitable for communicating with allocated channels through a plurality of through-electrodes. Each of the core dies may include: a through-electrode scan unit enabled according to allocated channel information, and suitable for performing a down scan of transmitting a signal downward through through-electrodes connected in a column direction among the through-electrodes and an up scan of transmitting a signal upward through the through-electrodes connected in the column direction; and a defect detection unit suitable for detecting whether the through-electrodes have a defect, based on the down scan and the up scan.

    Data output circuit and method for driving the same
    10.
    发明授权
    Data output circuit and method for driving the same 有权

    公开(公告)号：US09917585B2

    公开(公告)日：2018-03-13

    申请号：US13935931

    申请日：2013-07-05

    申请人： SK hynix Inc.

    发明人： Dong-Uk Lee

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017509

    摘要： A data output circuit includes a data driving unit suitable for driving a data transmission line with a driving voltage corresponding to data during a data transmission operation, and a charging/discharging unit suitable for storing charges on the data transmission line and reuse the stored charges as the driving voltage.