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    Clock stoppage in integrated circuits with multiple asynchronous clock domains
    11.
    发明授权
    Clock stoppage in integrated circuits with multiple asynchronous clock domains 有权

    公开(公告)号：US09600018B1

    公开(公告)日：2017-03-21

    申请号：US14300159

    申请日：2014-06-09

    Applicant: Xilinx, Inc.

    Inventor： Amitava Majumdar ,  Balakrishna Jayadev ,  Ismed D. Hartanto

    IPC: G06F1/00 ,  G06F1/12 ,  G06F1/06 ,  G06F1/10

    CPC classification number: G06F1/10 ,  G06F1/04 ,  G06F1/06 ,  G06F1/12

    Abstract: Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller.

    Testing for shorts between internal nodes of a power distribution grid
    12.
    发明授权
    Testing for shorts between internal nodes of a power distribution grid 有权
    测试配电网内部节点之间的短路

    公开(公告)号：US09453870B1

    公开(公告)日：2016-09-27

    申请号：US14252958

    申请日：2014-04-15

    Applicant: Xilinx, Inc.

    Inventor： Amitava Majumdar ,  Richard W. Swanson ,  Anna W. Wong ,  Suraj Ethirajan ,  Asim A. Bajwa ,  Jongheon Jeong

    IPC: G01R31/14 ,  G01R31/02

    CPC classification number: G01R31/021 ,  G01R19/2513 ,  G01R31/025 ,  G01R31/2853

    Abstract: In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

    Abstract translation: 在与IC芯片大致相关的装置中，IC芯片具有稳压电源，电源网格和测试电路。 稳压电源在源电源节点和源极接地节点之间偏置，源极接地节点是IC芯片的外部可访问节点。 电源网格的内部供电节点耦合到稳压电源。 测试电路耦合到电源网格的内部供电节点。 测试电路被配置为测试电源网格中的至少一个短路。 测试电路被配置为将电源网格的电力限制为小于探针尖端公差的电力。 测试电路被配置为在存在电源网格的背景电流泄漏的情况下测试至少一个短路。

    Scalable scan architecture for multi-circuit block arrays
    13.
    发明授权
    Scalable scan architecture for multi-circuit block arrays 有权

    公开(公告)号：US11639962B1

    公开(公告)日：2023-05-02

    申请号：US17199874

    申请日：2021-03-12

    Applicant: Xilinx, Inc.

    Inventor： Niravkumar Patel ,  Amitava Majumdar ,  Partho Tapan Chaudhuri

    IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27

    Abstract: An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.

    Efficient system debug infrastructure for tiled architecture
    14.
    发明授权
    Efficient system debug infrastructure for tiled architecture 有权

    公开(公告)号：US10110234B1

    公开(公告)日：2018-10-23

    申请号：US15654506

    申请日：2017-07-19

    Applicant: Xilinx, Inc.

    Inventor： Uma E. Durairajan ,  Subodh Kumar ,  Adam Elkins ,  Ghazaleh Mirjafari ,  Amitava Majumdar

    IPC: H03K19/177 ,  G01R31/3185

    Abstract: Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.

    Intra-chip and inter-chip data protection
    18.
    发明授权
    Intra-chip and inter-chip data protection 有权

    公开(公告)号：US12105658B2

    公开(公告)日：2024-10-01

    申请号：US17477185

    申请日：2021-09-16

    Applicant: XILINX, INC.

    Inventor： Pramod Bhardwaj ,  Sarosh I. Azad ,  Wern-Yan Koe ,  Amitava Majumdar

    IPC: G06F13/40 ,  G06F13/16 ,  G06F13/28

    CPC classification number: G06F13/4027 ,  G06F13/1668 ,  G06F13/28

    Abstract: In one example, an integrated circuit (IC) is provided that includes data circuitry and a processing circuitry. The data circuitry is configured to provide data to be transferred to a different circuitry within the IC or to an external IC. The processing circuitry is configured to: read the data provided by the data circuitry before it is transferred to the different circuitry or the external IC; calculate a first signature for the data; attach the first signature to the data; calculate, after transferring the data to the different circuitry or the external IC, a second signature for the data; extract the first signature corresponding to the data; compare the first signature to the second signature; and generate a signal based on a comparison of the first signature to the second signature.

    Testing memory elements using an internal testing interface
    19.
    发明授权
    Testing memory elements using an internal testing interface 有权

    公开(公告)号：US11500017B1

    公开(公告)日：2022-11-15

    申请号：US17216516

    申请日：2021-03-29

    Applicant: XILINX, INC.

    Inventor： Albert Shih-Huai Lin ,  Amitava Majumdar

    IPC: G01R31/3177 ,  G11C29/32 ,  G01R31/317 ,  G11C7/22 ,  G01R31/28 ,  G06F11/36 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/273 ,  G11C29/12

    Abstract: A semiconductor device comprises a plurality of memory elements, test control circuitry, and a testing interface. The test control circuitry is configure to determine that one or more clock signals associated with the memory elements have been stopped and generate a scan clock signal based on the determination that the one or more clock signals have been stopped. The test control circuitry is further configured to communicate the scan clock signal to the memory elements. The testing interface is configured to communicate test data from the memory elements. In one example, the test data is delimited with start and end marker elements. The semiconductor device is mounted to a circuit board and is communicatively coupled to communication pins of the circuit board.

    Restoring memory data integrity
    20.
    发明授权
    Restoring memory data integrity 有权

    公开(公告)号：US11429481B1

    公开(公告)日：2022-08-30

    申请号：US17178207

    申请日：2021-02-17

    Applicant: XILINX, INC.

    Inventor： Sarosh I. Azad ,  Wern-Yan Koe ,  Amitava Majumdar

    IPC: G06F11/10 ,  G06F12/06

    Abstract: Embodiments herein describe a hardware based scrubbing scheme where correction logic is integrated with memory elements such that scrubbing is performed by hardware. The correction logic reads the data words stored in the memory element during idle cycles. If a correctable error is detected, the correction logic can then use a subsequent idle cycle to perform a write to correct the error (i.e., replace the corrupted data stored in the memory element with corrected data). By using built-in or integrated correction logic, the embodiments herein do not add extra work for the processor, or can work with applications that do not include a processor. Further, because the correction logic scrubs the memory during idle cycles, correcting bit errors does not have a negative impact on the performance of the memory element. Memory scrubbing can delay the degradation of data error, extending the integrity of the data in the memory.

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