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    PERPENDICULAR MAGNETIC RANDOM-ACCESS MEMORY (MRAM) FORMATION BY DIRECT SELF-ASSEMBLY METHOD
    11.
    发明申请
    PERPENDICULAR MAGNETIC RANDOM-ACCESS MEMORY (MRAM) FORMATION BY DIRECT SELF-ASSEMBLY METHOD 审中-公开
    通过直接自组装方法形成的全磁性随机存取存储器（MRAM）

    公开(公告)号：US20160118577A1

    公开(公告)日：2016-04-28

    申请号：US14990911

    申请日：2016-01-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

    Abstract translation: 本公开的一些实施例涉及一种实现具有低于某些光刻技术的较低分辨率极限的最小尺寸的磁性随机存取存储器（MRAM）单元的基本均匀图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在位于基材表面上的异质结构上。 异质结构包括由绝缘层分开的第一和第二铁磁层。 将共聚物溶液自组装成包含第二聚合物种类的微畴图案的相分离材料在包含第一聚合物种类的聚合物基质内。 然后除去第一聚合物物质，留下第二聚合物物质的微畴图案。 通过在利用微畴图案作为硬掩模的同时蚀刻异质结构来形成异质结构内的磁记忆单元的图案。

    Silicon dot formation by direct self-assembly method for flash memory
    12.
    发明授权
    Silicon dot formation by direct self-assembly method for flash memory 有权
    通过闪存的直接自组装方法形成硅点

    公开(公告)号：US09281203B2

    公开(公告)日：2016-03-08

    申请号：US13974155

    申请日：2013-08-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Cheng-Te Lee ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L21/8239 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

    CPC classification number: H01L21/28273 ,  H01L21/31155 ,  H01L21/32105 ,  H01L21/32139 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of discrete storage elements comprising a substantially equal size within a memory cell. A copolymer solution comprising first and second polymer species is spin-coated onto a surface of a substrate and subjected to self-assembly into a phase-separated material comprising a regular pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first or second polymer species is then removed resulting with a pattern of micro-domains or the polymer matrix with a pattern of holes, which may be utilized as a hard-mask to form a substantially identical pattern of discrete storage elements through an etch, ion implant technique, or a combination thereof.

    Abstract translation: 本公开的一些实施例涉及一种实现在存储器单元内包括基本相等尺寸的离散存储元件的基本上均匀的图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在基材的表面上，并进行自组装成相分离的材料，该相分离材料包含第二聚合物物质的规则形式的第二聚合物种类的聚合物基质， 第一种聚合物种类。 然后去除第一或第二聚合物物质，其具有微畴图案或具有空穴图案的聚合物基质，其可以用作硬掩模，以通过蚀刻形成基本相同的离散存储元件图案， 离子注入技术或其组合。

    Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method
    13.
    发明授权
    Perpendicular magnetic random-access memory (MRAM) formation by direct self-assembly method 有权
    通过直接自组装方法形成垂直磁性随机存取存储器（MRAM）

    公开(公告)号：US09257636B2

    公开(公告)日：2016-02-09

    申请号：US14023552

    申请日：2013-09-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ming Chen ,  Chern-Yow Hsu ,  Szu-Yu Wang ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L43/12

    CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.

    Abstract translation: 本公开的一些实施例涉及一种实现具有低于某些光刻技术的较低分辨率极限的最小尺寸的磁性随机存取存储器（MRAM）单元的基本均匀图案的方法。 将包含第一和第二聚合物种类的共聚物溶液旋涂在位于基材表面上的异质结构上。 异质结构包括由绝缘层分开的第一和第二铁磁层。 将共聚物溶液自组装成包含第二聚合物种类的微畴图案的相分离材料在包含第一聚合物种类的聚合物基质内。 然后除去第一聚合物物质，留下第二聚合物物质的微畴图案。 通过在利用微畴图案作为硬掩模的同时蚀刻异质结构来形成异质结构内的磁记忆单元的图案。

    GaN Misfets with Hybrid AI203 As Gate Dielectric
    14.
    发明申请
    GaN Misfets with Hybrid AI203 As Gate Dielectric 有权
    作为栅极介质的混合AI203的GaN Misfets

    公开(公告)号：US20150060861A1

    公开(公告)日：2015-03-05

    申请号：US14016328

    申请日：2013-09-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  King-Yuen Wong ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L29/778 ,  H01L29/20 ,  H01L29/04 ,  H01L29/66

    CPC classification number: H01L29/7787 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462

    Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.

    Abstract translation: 本公开的一些实施例涉及具有良好的界面和体介电特性的混合栅极介电层。 表面捕集阱可能会降低器件性能，并在III-N HEMT中引起较大的阈值电压漂移。 本公开使用混合ALD（原子层沉积） - 氧化物层，其是基于H 2 O和O 3 / O 2的氧化物层的组合，其为III-N器件提供良好的界面和良好的体积介电性质。 H 2 O基氧化物层与III-N表面提供良好的界面，而O 3 / O 2基氧化物层提供良好的体积性质。

    Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric
    19.
    发明授权
    Gallium nitride transistor with a hybrid aluminum oxide layer as a gate dielectric 有权
    具有混合氧化铝层的氮化镓晶体管作为栅极电介质

    公开(公告)号：US09214539B2

    公开(公告)日：2015-12-15

    申请号：US14016328

    申请日：2013-09-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Chin Chiu ,  King-Yuen Wong ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

    IPC: H01L29/10 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/04

    CPC classification number: H01L29/7787 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66462

    Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.

    Abstract translation: 本公开的一些实施例涉及具有良好的界面和体介电特性的混合栅极介电层。 表面捕集阱可能会降低器件性能，并在III-N HEMT中引起较大的阈值电压漂移。 本公开使用混合ALD（原子层沉积） - 氧化物层，其是基于H 2 O和O 3 / O 2的氧化物层的组合，其为III-N器件提供良好的界面和良好的体积介电性质。 H 2 O基氧化物层与III-N表面提供良好的界面，而O 3 / O 2基氧化物层提供良好的体积性质。

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