公开(公告)号：US20230163183A1

公开(公告)日：2023-05-25

申请号：US18158192

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42364 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US20210273059A1

公开(公告)日：2021-09-02

申请号：US17324471

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/861

Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N(III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

公开(公告)号：US20210119011A1

公开(公告)日：2021-04-22

申请号：US17114715

申请日：2020-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L23/31 ,  H01L29/78

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

公开(公告)号：US20200098518A1

公开(公告)日：2020-03-26

申请号：US16180313

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Te Lee ,  Han-Chin Chiu

IPC: H01G4/10 ,  H01G4/30 ,  H01G4/20 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a laminated capacitor dielectric layer including alternating layers of high-k dielectric material and high-energy band gap material, and a method of formation. In some embodiments, the MIM capacitor has a laminated capacitor dielectric layer disposed over a capacitor bottom metal layer. The laminated capacitor dielectric layer includes a first layer of a first dielectric material, a second layer of a second dielectric material disposed on top of the first layer, a third layer of a third dielectric material disposed on top of the second layer, and a fourth layer of a fourth dielectric material disposed on top of the third layer. The first and third dielectric materials have a differing capacitance and band gap energy as compared to the second and fourth dielectric materials. A capacitor top metal layer is disposed over the laminated capacitor dielectric layer.

公开(公告)号：US20190393313A1

公开(公告)日：2019-12-26

申请号：US16562918

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/20 ,  H01L29/861 ,  H01L29/778 ,  H01L29/66

Abstract: The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

公开(公告)号：US09633920B2

公开(公告)日：2017-04-25

申请号：US14620428

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Cheng-Yuan Tsai ,  Ming-Wei Tsai ,  Yao-Wen Chang ,  Wen-Yuan Hsieh

IPC: H01L23/29 ,  H01L29/66 ,  H01L23/31 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/7787

Abstract: The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.

公开(公告)号：US09130026B2

公开(公告)日：2015-09-08

申请号：US14016302

申请日：2013-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Trinh Hai Dang ,  Hsing-Lien Lin ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7785 ,  H01L29/7787

Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).

Abstract translation: 本公开的一些实施方案涉及用于有效钝化III-N表面的晶体钝化层。 HEMT的表面钝化减少或消除了否则会降低器件性能的表面效应。 结晶钝化层降低了表面陷阱的降解效应，并且在III族氮化物表面和绝缘体之间提供良好的界面（例如，在钝化层上形成的栅极电介质）。

公开(公告)号：US20150123170A1

公开(公告)日：2015-05-07

申请号：US14583391

申请日：2014-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： King-Yuen Wong ,  Ming-Wei Tsai ,  Han-Chin Chiu

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/861

Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.

Abstract translation: 本公开涉及高电子迁移率晶体管兼容功率侧向场效应整流器（L-FER）装置。 在一些实施例中，整流器件在阳极端子和阴极端子之间的位置具有位于半导体材料层上方的电子供应层。 掺杂的III-N半导体材料层设置在电子供应层上。 钝化层位于电子供应层和掺杂的III-N半导体材料层之上。 栅极结构设置在掺杂的III-N半导体材料和钝化层的层上。 掺杂的III-N半导体材料层调制整流器件的阈值电压，而钝化层通过减轻由于高温反向偏压（HTRB）应力导致的电流劣化，提高了L-FER器件的可靠性。

公开(公告)号：US11984486B2

公开(公告)日：2024-05-14

申请号：US18158192

申请日：2023-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Chung-Yi Yu ,  Chen-Hao Chiang

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42364 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/2003

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

公开(公告)号：US20200098889A1

公开(公告)日：2020-03-26

申请号：US16695392

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/02 ,  H01L23/29 ,  H01L29/20 ,  H01L23/31 ,  H01L29/78

Abstract: Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.