公开(公告)号：US12027603B2

公开(公告)日：2024-07-02

申请号：US17857719

申请日：2022-07-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/66462 ,  H01L29/452 ,  H01L29/7786 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/41758

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.

公开(公告)号：US11901433B2

公开(公告)日：2024-02-13

申请号：US17410648

申请日：2021-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/66462 ,  H01L29/452 ,  H01L29/7786 ,  H01L29/1066 ,  H01L29/402 ,  H01L29/41758

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

公开(公告)号：US10134867B2

公开(公告)日：2018-11-20

申请号：US15947356

申请日：2018-04-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40

Abstract: A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer.

公开(公告)号：US09608060B2

公开(公告)日：2017-03-28

申请号：US14535110

申请日：2014-11-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chieh Chou ,  Tsai-Feng Yang ,  Chun-Yi Yang ,  Kun-Ming Huang ,  Shen-Ping Wang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC: H01L21/762 ,  H01L29/735 ,  H01L29/739 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/76283 ,  H01L29/7393 ,  H01L29/7394

Abstract: A semiconductor structure includes a substrate, a semiconductor device in the substrate, and an isolating structure in the substrate and adjacent to the semiconductor device. The isolating structure has a roughness surface at a sidewall of the isolating structure, and the roughness surface includes carbon atoms thereon.

公开(公告)号：US20150061007A1

公开(公告)日：2015-03-05

申请号：US14011991

申请日：2013-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Shou-Wei Lee ,  Shao-Chi Yu ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Po-Tao Chu

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/308 ,  H01L21/324 ,  H01L21/761 ,  H01L21/76224 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

Abstract: A high-voltage super junction device is disclosed. The device includes a semiconductor substrate region having a first conductivity type and having neighboring trenches disposed therein. The neighboring trenches each have trench sidewalls and a trench bottom surface. A region having a second conductivity type is disposed in or adjacent to a trench and meets the semiconductor substrate region at a p-n junction. A gate electrode is formed on the semiconductor substrate region and electrically is electrically isolated from the semiconductor substrate region by a gate dielectric. A body region having the second conductivity type is disposed on opposite sides of the gate electrode near a surface of the semiconductor substrate. A source region having the first conductivity type is disposed within in the body region on opposite sides of the gate electrode near the surface of the semiconductor substrate.

Abstract translation: 公开了一种高压超导装置。 该器件包括具有第一导电类型并且其中设置有相邻沟槽的半导体衬底区域。 相邻的沟槽各具有沟槽侧壁和沟槽底面。 具有第二导电类型的区域设置在沟槽中或与沟槽相邻并且在p-n结处与半导体衬底区域相遇。 栅极电极形成在半导体衬底区域上，并通过栅极电介质与半导体衬底区域电隔离。 具有第二导电类型的主体区域设置在靠近半导体衬底的表面的栅电极的相对侧上。 具有第一导电类型的源极区域设置在靠近半导体衬底的表面的栅电极的相对侧的体区内。

公开(公告)号：US11374107B2

公开(公告)日：2022-06-28

申请号：US16901555

申请日：2020-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/778 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, source and drain structures over the second III-V compound layer and spaced apart from each other, a gate structure over the second III-V compound layer and between the source and drain structures, a gate field plate over the second III-V compound layer and between the gate structure and the drain structure, and an etch stop layer over the drain structure and spaced apart from the gate field plate.

公开(公告)号：US10686054B2

公开(公告)日：2020-06-16

申请号：US16195683

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Hsin-Chih Lin ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu ,  Shen-Ping Wang ,  Chien-Li Kuo

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/778 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40

Abstract: A semiconductor device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a source contact and a drain contact over the second III-V compound layer, a gate contact over the second III-V compound layer and between the source contact and the drain contact, a gate field plate over the second III-V compound layer, a first etch stop layer over the source contact, and a second etch stop layer over the drain contact and separated from the first etch stop layer.

公开(公告)号：US08975153B2

公开(公告)日：2015-03-10

申请号：US13866102

申请日：2013-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Tzu-Cheng Chen ,  Ming-Che Yang ,  Po-Tao Chu

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0634

Abstract: A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Abstract translation: 一种形成半导体器件的方法包括在包括第一导电类型的半导体材料的衬底上形成硬掩模层，并且在硬掩模层中形成并延伸到衬底中的多个沟槽。 每个沟槽具有至少一个侧壁和底壁。 该方法还包括沿着每个沟槽的至少一个侧壁和底壁上形成至少一个阻挡绝缘体层，在每个沟槽的底壁上去除至少一个阻挡绝缘体层，并且将多个沟槽填充到 第二导电类型的半导体材料。

公开(公告)号：US20140322871A1

公开(公告)日：2014-10-30

申请号：US14330092

申请日：2014-07-14

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Long-Shih Lin ,  Fu-Hsiung Yang ,  Kun-Ming Huang ,  Ming-Yi Lin ,  Paul Chu

IPC: H01L29/66 ,  H01L21/308

CPC classification number: H01L21/308 ,  G01R31/129 ,  G01R31/2637 ,  H01L21/3083 ,  H01L21/76275 ,  H01L21/76283 ,  H01L29/086 ,  H01L29/66325 ,  H01L29/66689 ,  H01L29/7394 ,  H01L29/7824

Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

Abstract translation: 本公开的一些实施例涉及增加功率器件的击穿电压的方法。 功率器件形成在由器件晶片，手柄晶片和中间氧化物层构成的绝缘体上硅（SOI）晶片上。 在处理晶片的下表面上形成凹口，以限定处理晶片的凹陷区域。 处理晶片的凹陷区域具有大于零的第一处理晶片厚度。 处理晶片的未凹陷区域具有大于第一处理晶片厚度的第二处理晶片厚度。 凹陷区域的第一处理晶片厚度为功率器件提供了击穿电压的改善。

公开(公告)号：US09564515B2

公开(公告)日：2017-02-07

申请号：US14444861

申请日：2014-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jheng-Sheng You ,  Che-Yi Lin ,  Shen-Ping Wang ,  Kun-Ming Huang ,  Lieh-Chuan Chen ,  Po-Tao Chu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66712 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/7802

Abstract: A semiconductor device having a super junction structure includes a substrate, an epitaxial layer of a first conductivity type, a first trench, a first doped region of a second conductivity type opposite to the first conductivity type, a second trench and a second doped region of the first conductivity type. The epitaxial layer of the first conductivity type is over the substrate. The first trench is in the epitaxial layer. The first doped region of the second conductivity type is in the epitaxial layer and surrounds the first trench. The second trench is in the epitaxial layer and separated from the first trench. The second doped region of the first conductivity type is in the epitaxial layer and surrounds the second trench. The second doped region has a dopant concentration greater than a dopant concentration of the epitaxial layer. A method for manufacturing the semiconductor device is also provided.

Abstract translation: 具有超结结构的半导体器件包括衬底，第一导电类型的外延层，第一沟槽，与第一导电类型相反的第二导电类型的第一掺杂区，第二沟槽和第二掺杂区 第一种导电类型。 第一导电类型的外延层在衬底上。 第一沟槽在外延层中。 第二导电类型的第一掺杂区域在外延层中并围绕第一沟槽。 第二沟槽在外延层中并与第一沟槽分离。 第一导电类型的第二掺杂区域在外延层中并且包围第二沟槽。 第二掺杂区域的掺杂浓度大于外延层的掺杂剂浓度。 还提供了一种用于制造半导体器件的方法。