公开(公告)号：US20170250188A1

公开(公告)日：2017-08-31

申请号：US15054100

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

公开(公告)号：US09653302B2

公开(公告)日：2017-05-16

申请号：US14815386

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chia-Ming Pan ,  Chiang-Ming Chuang ,  Pei-Chi Ho ,  Ping-Pang Hsieh

IPC: H01L21/28 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

公开(公告)号：US09263316B2

公开(公告)日：2016-02-16

申请号：US14179659

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Shang-Yen Wu ,  Chiang-Ming Chuang ,  Ping-Pang Hsieh

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02274 ,  H01L21/31055

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide.

Abstract translation: 提供半导体器件。 半导体器件包括半导体衬底和沟槽隔离。 在半导体衬底中形成沟槽隔离，并且包括隔离氧化物和旋涂材料。 隔离氧化物被半导体衬底周边封闭。 旋涂层由隔离氧化物外围封闭。

公开(公告)号：US11925017B2

公开(公告)日：2024-03-05

申请号：US16740499

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H10B41/50 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/30 ,  H10B41/42 ,  H10B41/47

CPC classification number: H10B41/30 ,  H01L21/32135 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

公开(公告)号：US10658479B2

公开(公告)日：2020-05-19

申请号：US16191085

申请日：2018-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsien Chu ,  Chiang-Ming Chuang ,  Cheng-Huan Chung

IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/321 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/788 ,  H01L27/11534 ,  H01L27/11524

Abstract: The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.

公开(公告)号：US20200152648A1

公开(公告)日：2020-05-14

申请号：US16740499

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11519 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11531 ,  H01L27/11541

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

公开(公告)号：US09947759B1

公开(公告)日：2018-04-17

申请号：US15471277

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Shih Lin ,  Chiang-Ming Chuang ,  Kun-Tsang Chuang ,  Yung-Lung Hsu

IPC: H01L29/788 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4983 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a semiconductor substrate. A first structure and a second structure are respectively disposed on the semiconductor substrate and connected to each other. The second structure includes a limiting layer disposed on the upper surface of the semiconductor substrate, a first polysilicon layer disposed conformally on the limiting layer and the semiconductor substrate, and a second polysilicon layer disposed conformally on the first polysilicon layer. A ridge of the second polysilicon layer is disposed near an edge of the second structure beside the first structure, vertically aligned with the limiting layer and defined as a limiting block. A bottom anti-reflection coating (BARC) layer of a low-viscosity material blanketly overlying a top surface of the second structure has an external surface substantially parallel to the top surface of the second structure.

公开(公告)号：US20180047740A1

公开(公告)日：2018-02-15

申请号：US15236531

申请日：2016-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ming Lee ,  Chiang-Ming Chuang ,  Kun-Tsang Chuang ,  Yung-Lung Hsu ,  Hsin-Chi Chen

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L21/28273 ,  H01L27/11548 ,  H01L29/42328

Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region.

公开(公告)号：US20180151519A1

公开(公告)日：2018-05-31

申请号：US15405384

申请日：2017-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Szu-Hsien LU ,  Chiang-Ming Chuang

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L2224/02215 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059

Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer.

公开(公告)号：US09899395B1

公开(公告)日：2018-02-20

申请号：US15219497

申请日：2016-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ming Lee ,  Po-Wei Liu ,  Chiang-Ming Chuang ,  Yung-Lung Hsu ,  Hsin-Chi Chen

IPC: H01L29/423 ,  H01L27/11521 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L27/11521 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/42368 ,  H01L2924/1438

Abstract: A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.