公开(公告)号：US11925017B2

公开(公告)日：2024-03-05

申请号：US16740499

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H10B41/50 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10 ,  H10B41/30 ,  H10B41/42 ,  H10B41/47

CPC classification number: H10B41/30 ,  H01L21/32135 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/10 ,  H10B41/42 ,  H10B41/47

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

公开(公告)号：US20200152648A1

公开(公告)日：2020-05-14

申请号：US16740499

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11519 ,  H01L21/3213 ,  H01L21/28 ,  H01L27/11531 ,  H01L27/11541

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

公开(公告)号：US11462639B2

公开(公告)日：2022-10-04

申请号：US16727494

申请日：2019-12-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Pan ,  Chia-Ta Hsieh ,  Po-Wei Liu ,  Yun-Chi Wu

IPC: H01L29/78 ,  H01L29/66

Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.

公开(公告)号：US11282931B2

公开(公告)日：2022-03-22

申请号：US16879559

申请日：2020-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu Lin ,  Chi-Chung Jen ,  Chia-Ming Pan ,  Su-Yu Yeh ,  Keng-Ying Liao ,  Chih-Wei Sung

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A memory device includes a floating gate, a control gate, a spacer structure, a dielectric layer, and an erase gate. The floating gate is above a substrate. The floating gate has a curved sidewall. The control gate is above the floating gate. The spacer structure is in contact with the control gate and the floating gate. The spacer structure is spaced apart from the curved sidewall of the floating gate. The dielectric layer is in contact with the spacer structure and the curved sidewall of the floating gate. The erase gate is above the dielectric layer.

公开(公告)号：US10103235B2

公开(公告)日：2018-10-16

申请号：US15592329

申请日：2017-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Pan ,  Chiang-Ming Chuang ,  Pei-Chi Ho ,  Ping-Pang Hsieh

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

公开(公告)号：US20170250188A1

公开(公告)日：2017-08-31

申请号：US15054100

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788

Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

公开(公告)号：US09653302B2

公开(公告)日：2017-05-16

申请号：US14815386

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chia-Ming Pan ,  Chiang-Ming Chuang ,  Pei-Chi Ho ,  Ping-Pang Hsieh

IPC: H01L21/28 ,  H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66553 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

公开(公告)号：US10535670B2

公开(公告)日：2020-01-14

申请号：US15054100

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsuan Liu ,  Chiang-Ming Chuang ,  Chih-Ming Lee ,  Kun-Tsang Chuang ,  Hung-Che Liao ,  Chia-Ming Pan ,  Hsin-Chi Chen

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L27/11521 ,  H01L21/28 ,  H01L27/11531 ,  H01L27/11541 ,  H01L21/3213 ,  H01L27/11519 ,  H01L29/66

Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

公开(公告)号：US11855201B2

公开(公告)日：2023-12-26

申请号：US17952940

申请日：2022-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Pan ,  Chia-Ta Hsieh ,  Po-Wei Liu ,  Yun-Chi Wu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/66681

Abstract: A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

公开(公告)号：US11804529B2

公开(公告)日：2023-10-31

申请号：US17698748

申请日：2022-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chu Lin ,  Chi-Chung Jen ,  Chia-Ming Pan ,  Su-Yu Yeh ,  Keng-Ying Liao ,  Chih-Wei Sung

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788 ,  H10B41/30

CPC classification number: H01L29/42328 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881 ,  H10B41/30

Abstract: A method includes depositing a gate dielectric film over a substrate. A floating gate layer and a control gate layer are deposited over the gate dielectric film. The control gate layer is patterned to form a control gate over the floating gate layer. A top portion of the floating gate layer is patterned. A spacer structure is formed on a sidewall of the control gate and over a remaining portion of the floating gate layer. The remaining portion of the floating gate layer is patterned to form a bottom portion of a floating gate. A ratio of the bottom width of the bottom portion to the middle width of the bottom portion is in a range between about 103% and about 108%. The gate dielectric film is patterned form a gate dielectric layer.