知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

23 records (took 0.017 seconds)

    Manufacturing method of semiconductor device
    1.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US10825914B2

    公开(公告)日：2020-11-03

    申请号：US16180026

    申请日：2018-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Chuan Lin ,  Chiang-Ming Chuang ,  Shang-Yen Wu

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/11546 ,  H01L29/423 ,  H01L21/321

    Abstract: A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20190148513A1

    公开(公告)日：2019-05-16

    申请号：US16180026

    申请日：2018-11-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Chuan Lin ,  Chiang-Ming Chuang ,  Shang-Yen Wu

    IPC: H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/762

    Abstract: A method of manufacturing a semiconductor device includes following steps. The substrate has a dummy region and a memory cell region. A plurality of first stack structures are formed over the substrate in the memory cell region. At least one second stack structure is formed over the substrate in the dummy region. A conductive layer is formed over the substrate to cover the first stack structures and the at least one second stack structure. A planarization process is performed on the conductive layer to expose top surfaces of the first stack structures and the at least one second stack structure. The conductive layer is patterned to form an erase gate between adjacent two first stack structures, and to form first and second select gates outside the adjacent two first stack structures.

    Semiconductor Device With Shallow Trench Isolation
    7.
    发明申请
    Semiconductor Device With Shallow Trench Isolation 有权
    具有浅沟槽隔离的半导体器件

    公开(公告)号：US20150228534A1

    公开(公告)日：2015-08-13

    申请号：US14179659

    申请日：2014-02-13

    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

    Inventor： Shang-Yen Wu ,  Chiang-Ming Chuang ,  Ping-Pang Hsieh

    IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/06

    CPC classification number: H01L21/76224 ,  H01L21/02274 ,  H01L21/31055

    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is formed in the semiconductor substrate, and includes an isolation oxide and a spin coating material. The isolation oxide is peripherally enclosed by the semiconductor substrate. The spin coating material is peripherally enclosed by the isolation oxide.

    Abstract translation: 提供半导体器件。 半导体器件包括半导体衬底和沟槽隔离。 在半导体衬底中形成沟槽隔离，并且包括隔离氧化物和旋涂材料。 隔离氧化物被半导体衬底周边封闭。 旋涂层由隔离氧化物外围封闭。

    Gate structure with multiple spacers
    10.
    发明授权
    Gate structure with multiple spacers 有权

    公开(公告)号：US10103235B2

    公开(公告)日：2018-10-16

    申请号：US15592329

    申请日：2017-05-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chia-Ming Pan ,  Chiang-Ming Chuang ,  Pei-Chi Ho ,  Ping-Pang Hsieh

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11521

    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

Patent Agency Ranking