公开(公告)号：US20240386919A1

公开(公告)日：2024-11-21

申请号：US18786289

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Meng-Sheng Chang ,  Tung-Cheng Chang ,  Yih Wang

IPC: G11C5/14 ,  G11C7/10 ,  G11C17/16 ,  G11C17/18

Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N NMOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.

公开(公告)号：US20240292609A1

公开(公告)日：2024-08-29

申请号：US18660794

申请日：2024-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Shao-Yu Chou ,  Yih Wang

IPC: H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L23/528 ,  H01L23/532

CPC classification number: H10B20/20 ,  G06F30/392 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53271

Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.

公开(公告)号：US12062408B2

公开(公告)日：2024-08-13

申请号：US18361542

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C5/06

CPC classification number: G11C5/063

Abstract: Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.

公开(公告)号：US20240090231A1

公开(公告)日：2024-03-14

申请号：US18516908

申请日：2023-11-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Yi-Ching Liu ,  Sai-Hooi Yeong ,  Yih Wang ,  Yu-Ming Lin

IPC: H10B51/40 ,  G11C11/22 ,  H01L23/522 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H10B51/20 ,  H10B51/30 ,  H10B51/50

CPC classification number: H10B51/40 ,  G11C11/2257 ,  H01L23/5226 ,  H10B43/30 ,  H10B43/40 ,  H10B43/50 ,  H10B51/20 ,  H10B51/30 ,  H10B51/50

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

公开(公告)号：US11915787B2

公开(公告)日：2024-02-27

申请号：US17815113

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bo-Feng Young ,  Yu-Ming Lin ,  Shih-Lien Linus Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Chia-En Huang ,  Yih Wang

IPC: G11C7/12 ,  G06F30/39 ,  G11C8/08

CPC classification number: G11C7/12 ,  G06F30/39 ,  G11C8/08

Abstract: An integrated circuit (IC) device includes a substrate, and a memory array layer having a plurality of transistors. First through fourth gate contacts are arranged along a first axis, and coupled to underlying gates of the plurality of transistors. First through fifth source/drain contacts in the memory array layer extend along a second axis transverse to the first axis, and are coupled to underlying source/drains of the plurality of transistors. The gate contacts and the source/drain contacts are alternatingly arranged along the first axis. A source line extends along the first axis, and is coupled to the first and fifth source/drain contacts. First and second word lines extend along the first axis, the first word line is coupled to the first and third gate contacts, and the second word line is coupled to the second and fourth gate contacts.

公开(公告)号：US11903188B2

公开(公告)日：2024-02-13

申请号：US17673126

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US20240021220A1

公开(公告)日：2024-01-18

申请号：US18361542

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C5/06

CPC classification number: G11C5/063

Abstract: Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.

公开(公告)号：US11854616B2

公开(公告)日：2023-12-26

申请号：US17460206

申请日：2021-08-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/10 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/003 ,  G11C13/0026 ,  G11C13/0028

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

公开(公告)号：US11842781B2

公开(公告)日：2023-12-12

申请号：US17567705

申请日：2022-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang ,  Shao-Yu Chou ,  Yih Wang

IPC: G11C17/16 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18 ,  G06F21/79 ,  G06F12/14

CPC classification number: G11C17/16 ,  G06F12/14 ,  G06F21/79 ,  G11C7/24 ,  G11C8/14 ,  G11C17/18

Abstract: A layout method includes: forming a layout structure of a memory array having first and second rows, each including a plurality of storage cells, wherein at least one of the storage cells includes a fuse; disposing a word line between the first and second rows; disposing a plurality of control electrodes across the word line for connecting the storage cells of the first row and the storage cells of the second row respectively; disposing a first cut layer on a first control electrode of the control electrodes located on a first side of the word line; and disposing a second cut layer on a second control electrode of the control electrodes located on a second side of the word line; wherein the first side of the word line is opposite to the second side of the word line.

公开(公告)号：US20230386538A1

公开(公告)日：2023-11-30

申请号：US18446999

申请日：2023-08-09

Applicant: Taiwan Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/12 ,  G11C5/14 ,  H01L27/06 ,  G11C5/02

CPC classification number: G11C7/12 ,  G11C5/14 ,  H01L27/0688 ,  G11C5/025

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.