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    Balanced negative bitline voltage for a write assist circuit
    1.
    发明授权
    Balanced negative bitline voltage for a write assist circuit 有权

    公开(公告)号：US12087345B2

    公开(公告)日：2024-09-10

    申请号：US17542938

    申请日：2021-12-06

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Che Tsai ,  Chia-En Huang ,  Chia-Cheng Chen ,  Yih Wang

    IPC: G11C11/24 ,  G11C7/12 ,  G11C11/419

    CPC classification number: G11C11/24 ,  G11C7/12 ,  G11C11/419

    Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.

    MEMORY DEVICE
    4.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210350847A1

    公开(公告)日：2021-11-11

    申请号：US16870030

    申请日：2020-05-08

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hidehiro Fujiwara ,  Chia-En Huang ,  Yen-Huei Chen ,  Jui-Che Tsai ,  Yih Wang

    IPC: G11C11/419 ,  G11C7/12

    Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

    SRAM POWER-UP RANDOM NUMBER GENERATOR
    5.
    发明申请
    SRAM POWER-UP RANDOM NUMBER GENERATOR 有权

    公开(公告)号：US20210350845A1

    公开(公告)日：2021-11-11

    申请号：US17359994

    申请日：2021-06-28

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Jui-Che Tsai ,  Chen-Lin Yang ,  Yu-Hao Hsu ,  Shih-Lien Linus Lu

    IPC: G11C11/418 ,  G11C7/12 ,  G06F7/58 ,  G11C5/14 ,  G11C8/08

    Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.

    Method of writing to and reading data from a three-dimensional two port register file
    7.
    发明授权
    Method of writing to and reading data from a three-dimensional two port register file 有权
    从三维二端口寄存器文件写入和读取数据的方法

    公开(公告)号：US09275724B2

    公开(公告)日：2016-03-01

    申请号：US14666373

    申请日：2015-03-24

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Ching-Wei Wu ,  Jui-Che Tsai

    IPC: G11C8/00 ,  G11C11/418 ,  G11C7/18 ,  G11C11/419 ,  G11C13/00 ,  G11C11/412

    CPC classification number: G11C11/418 ,  G11C7/18 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0023

    Abstract: A method comprises selecting a memory cell included in a memory cell array in which data is to be stored. The memory cell array is connected with a logic gate array. The memory cells of the memory cell array are individually coupled with a corresponding logic gate of the logic gate array by a separate word line output. The method also comprises communicating a write row output signal to the logic gate array. The write row output signal is communicated from a write address row decoder to the logic gate array. The write address row decoder has a plurality of write row outputs coupled with the logic gate array. The method further comprises communicating a write column output signal to the logic gate array. The write column output signal is communicated from a write address column decoder to the logic gate array.

    Abstract translation: 一种方法包括选择包含在其中要存储数据的存储单元阵列中的存储单元。 存储单元阵列与逻辑门阵列连接。 存储单元阵列的存储单元通过单独的字线输出与逻辑门阵列的对应逻辑门单独耦合。 该方法还包括将写入行输出信号传送到逻辑门阵列。 写入行输出信号从写入地址行解码器传送到逻辑门阵列。 写地址行解码器具有与逻辑门阵列耦合的多个写行输出。 该方法还包括将写入列输出信号传送到逻辑门阵列。 写列输出信号从写地址列解码器传送到逻辑门阵列。

    Three-dimensional two port register file
    8.
    发明授权
    Three-dimensional two port register file 有权
    三维二端口注册文件

    公开(公告)号：US09001611B1

    公开(公告)日：2015-04-07

    申请号：US14069411

    申请日：2013-11-01

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Ching-Wei Wu ,  Jui-Che Tsai

    IPC: G11C8/00 ,  G11C11/418

    CPC classification number: G11C11/418 ,  G11C7/18 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0023

    Abstract: An integrated circuit that includes an array of memory cells. The integrated circuit also includes a write address row decoder having a plurality of write row outputs and a write address column decoder having a plurality of write column outputs. A write logic array is electrically connected to the write row outputs and the write column outputs and has a separate write word line (WWL) output electrically connected to each cell in the array of memory cells.

    Abstract translation: 包括存储器单元阵列的集成电路。 集成电路还包括具有多个写入行输出的写入地址行解码器和具有多个写入列输出的写入地址列解码器。 写入逻辑阵列电连接到写入行输出和写入列输出，并且具有电连接到存储器单元阵列中的每个单元的单独写入字线（WWL）输出。

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