公开(公告)号：US11903188B2

公开(公告)日：2024-02-13

申请号：US17673126

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US12284804B2

公开(公告)日：2025-04-22

申请号：US18404849

申请日：2024-01-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  G11C17/18 ,  H10B20/25

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

公开(公告)号：US11658114B2

公开(公告)日：2023-05-23

申请号：US17229345

申请日：2021-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Ting Wu ,  Meng-Sheng Chang ,  Shao-Yu Chou ,  Chung-I Huang

IPC: H01L23/525 ,  H01L27/112 ,  H01L21/3213

CPC classification number: H01L23/5256 ,  H01L27/11206 ,  H01L21/32139

Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.

公开(公告)号：US12237264B2

公开(公告)日：2025-02-25

申请号：US18322481

申请日：2023-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Ting Wu ,  Meng-Sheng Chang ,  Shao-Yu Chou ,  Chung-I Huang

IPC: H01L23/525 ,  H10B20/25 ,  H01L21/3213

Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.

公开(公告)号：US12190949B2

公开(公告)日：2025-01-07

申请号：US18316442

申请日：2023-05-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Perng-Fei Yuh ,  Shao-Ting Wu ,  Yu-Fan Lin

IPC: G11C11/16 ,  G11C7/14 ,  G11C13/00

Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

公开(公告)号：US20250071986A1

公开(公告)日：2025-02-27

申请号：US18518809

申请日：2023-11-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shao-Ting Wu ,  Meng-Sheng Chang

IPC: H10B20/25 ,  G11C17/16

Abstract: A memory device is disclosed. The memory device includes a memory array comprising a plurality of memory cells. At least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit. At least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit.

公开(公告)号：US12205891B2

公开(公告)日：2025-01-21

申请号：US17885321

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Ting Wu ,  Meng-Sheng Chang ,  Shao-Yu Chou ,  Chung-I Huang

IPC: H01L23/525 ,  H10B20/25 ,  H01L21/3213

Abstract: A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.

公开(公告)号：US11651819B2

公开(公告)日：2023-05-16

申请号：US17209965

申请日：2021-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Perng-Fei Yuh ,  Shao-Ting Wu ,  Yu-Fan Lin

IPC: G11C13/00 ,  G11C11/16 ,  G11C7/14

CPC classification number: G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1697

Abstract: A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.