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公开(公告)号：US20250120074A1
公开(公告)日：2025-04-10
申请号：US18484237
申请日：2023-10-10
Inventor： Meng-Sheng Chang , Chia-En Huang , Yih Wang
Abstract: A memory device including a substrate, a sense amplifier that includes first gate-all-around transistors that have first drain/source regions that extend into the substrate, and bit cells that include fuse memory elements and second gate-all-around transistors. Each of the bit cells includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to a second gate-all-around transistor that includes second drain/source regions and a bottom dielectric isolation layer under the second drain/source regions.
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公开(公告)号：US20250120058A1
公开(公告)日：2025-04-10
申请号：US18982150
申请日：2024-12-16
Inventor： Meng-Sheng Chang , Chia-En Huang , Yi-Hsun Chiu , Yih Wang
IPC: H10B10/00
Abstract: A memory cell is disclosed. The memory cell includes a first transistor. The first transistor includes a first conduction channel collectively constituted by one or more first nanostructures spaced apart from one another along a vertical direction. The memory cell includes a second transistor electrically coupled to the first transistor in series. The second transistor includes a second conduction channel collectively constituted by one or more second nanostructures spaced apart from one another along the vertical direction. At least one of the one or more first nanostructures is applied with first stress by a first metal structure extending, along the vertical direction, into a first drain/source region of the first transistor.
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公开(公告)号：US20250118367A1
公开(公告)日：2025-04-10
申请号：US18938961
申请日：2024-11-06
Inventor： Hiroki Noguchi , Yu-Der Chih , Yih Wang
Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
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公开(公告)号：US12260928B2
公开(公告)日：2025-03-25
申请号：US17835652
申请日：2022-06-08
Inventor： Nail Etkin Can Akkaya , Mahmut Sinangil , Yih Wang , Jonathan Tsung-Yung Chang
IPC: G11C5/14 , G11C7/12 , G11C11/419 , H10B10/00
Abstract: A device includes a memory array formed on a front side of a substrate. The memory array is accessible through a plurality of bit lines. The memory device includes a switch transistor formed on the front side of the substrate. The switch transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on a back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines, in response to the switch transistor being turned off.
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公开(公告)号：US12254923B2
公开(公告)日：2025-03-18
申请号：US18149149
申请日：2023-01-02
Inventor： Perng-Fei Yuh , Jui-Che Tsai , Hiroki Noguchi , Yih Wang
IPC: G11C16/04 , G11C11/16 , G11C11/412 , G11C11/418 , G11C11/419 , G11C14/00
Abstract: A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.
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Patent Agency Ranking
公开(公告)号：US12218047B2
公开(公告)日：2025-02-04
申请号：US18514796
申请日：2023-11-20
Inventor： Meng-Sheng Chang , Chia-En Huang , Yi-Hsun Chiu , Yih Wang
IPC: H01L23/525 , G11C17/16 , G11C17/18 , H10B20/25
Abstract: A memory device includes a programming transistor and a reading transistor of an anti-fuse memory cell. The programming transistor includes first semiconductor nanostructures vertically spaced apart from one another, each of the first semiconductor nanostructures having a first width along a first lateral direction. The reading transistor includes second semiconductor nanostructures vertically spaced apart from one another, each of the second semiconductor nanostructures having a second width different from the first width along the second direction. The memory device also includes a first and a second gate metals. The first gate metal wraps around each of the first semiconductor nanostructures with a first gate dielectric disposed therein. The second gate metal wraps around each of the second semiconductor nanostructures with a second gate dielectric disposed therein.
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公开(公告)号：US12210368B2
公开(公告)日：2025-01-28
申请号：US18599233
申请日：2024-03-08
Inventor： Perng-Fei Yuh , Yoshitaka Yamauchi , Yih Wang
Abstract: The present disclosure provides a bias generating device and a method for generating bias. A bias generating device includes a first diode-connected transistor pair connected to receive a first voltage; a second diode-connected transistor pair connected to receive a second voltage; and a first transistor pair connected to the first diode-connected transistor pair and the second diode-connected transistor pair. The first transistor pair is configured to generate a third voltage in response to the first voltage and the second voltage.
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公开(公告)号：US12176049B2
公开(公告)日：2024-12-24
申请号：US18362223
申请日：2023-07-31
Inventor： Meng-Sheng Chang , Chia-En Huang , Yih Wang
Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.
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公开(公告)号：US20240389347A1
公开(公告)日：2024-11-21
申请号：US18789156
申请日：2024-07-30
Inventor： Chia-Ta Yu , Chia-En Huang , Yi-Ching Liu , Yih Wang , Sai-Hooi Yeong , Yu-Ming Lin
Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.
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公开(公告)号：US20240389332A1
公开(公告)日：2024-11-21
申请号：US18780425
申请日：2024-07-22
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC: H10B51/20 , G11C5/06 , G11C11/22 , H01L23/522
Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
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