公开(公告)号：US20150048488A1

公开(公告)日：2015-02-19

申请号：US13968174

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Yun Peng ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Kuang-Yuan Hsu

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure.

Abstract translation: 公开了半导体器件，其制造方法和IMD结构。 在一些实施例中，半导体器件包括设置在工件上的粘附层。 粘合层具有约4.0或更小的介电常数并且包括基本均匀的材料。 绝缘材料层设置在粘合层上。 绝缘材料层的介电常数为2.6以下。 粘合层和绝缘材料层包括IMD结构。

公开(公告)号：US11069558B2

公开(公告)日：2021-07-20

申请号：US16713981

申请日：2019-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US09812390B2

公开(公告)日：2017-11-07

申请号：US15157033

申请日：2016-05-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hui-Chun Yang ,  Mei-Ling Chen ,  Keng-Chu Lin ,  Joung-Wei Liou

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/28562 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

公开(公告)号：US09564383B2

公开(公告)日：2017-02-07

申请号：US14733573

申请日：2015-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/31 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

Abstract translation: 提供了一种用于低k电介质层的系统和方法。 优选的实施方案包括形成基质并在基质内形成致孔剂。 致孔剂包括具有少于15个碳原子和大量单键的有机环结构。 此外，致孔剂可能具有大于1.3的粘度和小于0.5的雷诺数。

公开(公告)号：US09341945B2

公开(公告)日：2016-05-17

申请号：US13973512

申请日：2013-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Keng-Chu Lin ,  Joung-Wei Liou ,  Cheng-Han Wu ,  Ya Hui Chang

IPC: G03F7/004 ,  G03F7/038 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  G03F7/039 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/0388 ,  G03F7/038 ,  G03F7/0382 ,  G03F7/0397 ,  G03F7/11 ,  G03F7/167 ,  G03F7/2041 ,  G03F7/322 ,  G03F7/325 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/32139

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Abstract translation: 提供了一种用于沉积光致抗蚀剂并利用光致抗蚀剂的系统和方法。 在一个实施方案中，使用沉积室以及包含碳 - 碳双键的第一前体材料和包含将光致抗蚀剂沉积到基底上的重复单元的第二前体材料。 第一前体材料在被引入沉积室之前在远程等离子体室中变成等离子体。 得到的光致抗蚀剂包括具有碳 - 碳双键的碳骨架。

公开(公告)号：US20130337651A1

公开(公告)日：2013-12-19

申请号：US13971600

申请日：2013-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Chi Ko ,  Chih-Hao Chen ,  Keng-Chu Lin

IPC: H01L21/311

CPC classification number: H01L21/31105 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832

Abstract: A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.

Abstract translation: 光刻图案的方法包括在材料层上形成第一蚀刻停止层，第二蚀刻停止层和硬掩模层。 通过在第二蚀刻停止层，第一蚀刻停止层和材料层之间存在材料梯度组成的方式来选择第一蚀刻停止层和第二蚀刻停止层的材料。 因此，在蚀刻工艺中实现第二蚀刻停止层，第一蚀刻停止层和材料层之间的梯度蚀刻速率，以在第二和第一蚀刻停止层内形成具有平滑和/或垂直侧壁的蚀刻图案，并且 材料层。

公开(公告)号：US20240387653A1

公开(公告)日：2024-11-21

申请号：US18789553

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mrunal Abhijith KHADERBAD ,  Keng-Chu Lin ,  Yu-Yun Peng

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

公开(公告)号：US20240355733A1

公开(公告)日：2024-10-24

申请号：US18303588

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Zheng-Yong Liang ,  Wei-Ting Yeh ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/373 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76898 ,  H01L23/3738 ,  H01L23/5226

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

公开(公告)号：US11996363B2

公开(公告)日：2024-05-28

申请号：US17473573

申请日：2021-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/373 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/3736 ,  H01L23/5283 ,  H01L23/53228

Abstract: An interconnect structure, along with methods of forming such, are described. In some embodiments, the structure includes a first dielectric layer disposed over one or more devices, a first conductive feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first conductive feature, and a second conductive feature disposed in the second dielectric layer. The second conductive feature is electrically connected to the first conductive feature. The structure further includes a heat dissipation layer disposed between the first and second dielectric layers, and the heat dissipation layer partially surrounds the second conductive feature and is electrically isolated from the first and second conductive features.

公开(公告)号：US20210083119A1

公开(公告)日：2021-03-18

申请号：US16572812

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mrunal A. Khaderbad ,  Keng-Chu Lin ,  Sung-Li Wang

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66

Abstract: A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.