公开(公告)号：US11887936B2

公开(公告)日：2024-01-30

申请号：US17469952

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyong Kim ,  Sungwon Shin ,  Seungmin Lee ,  Juyoung Lim ,  Wonseok Cho

IPC: H01L23/544 ,  H01L23/532 ,  H01L23/528 ,  H10B41/46

CPC classification number: H01L23/544 ,  H01L23/5283 ,  H01L23/53295 ,  H10B41/46

Abstract: A semiconductor device includes a first stack structure on a substrate, and a second stack structure on the first stack structure. A channel structure extends through the first stack structure and the second stack structure. A first auxiliary stack structure including a plurality of first insulating layers and a plurality of first mold layers are alternately stacked on the substrate. An alignment key extends into the first auxiliary stack structure and protrudes to a higher level than an uppermost end of the first stack structure. A second auxiliary stack structure is disposed on the first auxiliary stack structure and the alignment key, and includes a plurality of second insulating layers and a plurality of second mold layers alternately stacked. The second auxiliary stack structure includes a protrusion aligned with the alignment key.

公开(公告)号：US11437396B2

公开(公告)日：2022-09-06

申请号：US17032128

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20200348599A1

公开(公告)日：2020-11-05

申请号：US16676588

申请日：2019-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunhee Bai ,  Jinhong Park ,  Jinseok Heo ,  Seungmin Lee ,  Suntaek Lim

IPC: G03F7/20 ,  H01L21/268

Abstract: Disclosed are a system for fabricating a semiconductor device and a method of fabricating a semiconductor device. The system may include a chamber, an extreme ultraviolet (EUV) source in the chamber and configured to generate an EUV beam, an optical system on the EUV source and configured to provide the EUV beam to a substrate, a substrate stage in the chamber and configured to receive the substrate, a reticle stage in the chamber and configured to hold a reticle that is configured to project the EUV beam onto the substrate, and a particle collector between the reticle and the optical system and configured to allow for a selective transmission of the EUV beam and to remove a particle.

公开(公告)号：US12133384B2

公开(公告)日：2024-10-29

申请号：US18352182

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/20 ,  H10B43/30 ,  H10B43/40

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20240312938A1

公开(公告)日：2024-09-19

申请号：US18674610

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Seungmin Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L23/5226 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer.

公开(公告)号：US20240274416A1

公开(公告)日：2024-08-15

申请号：US18430475

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesik An ,  Dongig Oh ,  Thanh Cuong Nguyen ,  Suntaek Lim ,  Seungmin Lee ,  Inkook Jang ,  Joohyun Jeon

IPC: H01J37/32 ,  H01J37/34

CPC classification number: H01J37/32926 ,  H01J37/3476 ,  H01J2237/24585 ,  H01J2237/332

Abstract: Provided is a plasma process simulation method including defining a plasma reaction for a wafer, calculating a reaction parameter of the plasma reaction, and generating a plasma process simulation profile based on a calculated reaction parameter. The reaction parameter are set based on a physical reaction and a chemical reaction.

公开(公告)号：US11737270B2

公开(公告)日：2023-08-22

申请号：US17897255

申请日：2022-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Jisung Cheon ,  Yoonhwan Son ,  Seungmin Lee

IPC: H10B43/20 ,  H10B43/30 ,  H10B43/40

CPC classification number: H10B43/20 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20230080606A1

公开(公告)日：2023-03-16

申请号：US17852812

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee ,  Junhyoung Kim ,  Kangmin Kim ,  Joonsung Lim

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.

公开(公告)号：US20220375862A1

公开(公告)日：2022-11-24

申请号：US17563275

申请日：2021-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kangmin Kim ,  Taemin Eom ,  Seungmin Lee ,  Changsun Hwang

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a substrate including a cell array region and a contact region; a plurality of gate electrodes arranged on the substrate in a first direction perpendicular to an upper surface of the substrate, the plurality of gate electrodes being extending in the cell array region and the contact region; a plurality of channel structures penetrating the plurality of gate electrodes in the first direction in the cell array region; a plurality of dummy channel structures penetrating the plurality of gate electrodes in the first direction in the contact region; a plurality of cell gate contacts extending in the first direction and each electrically connected to a respective one of the plurality of gate electrodes in the contact region; and a plurality of dummy contacts extending in the first direction on the plurality of dummy channel structures.

公开(公告)号：US20220367359A1

公开(公告)日：2022-11-17

申请号：US17567249

申请日：2022-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kangmin Kim ,  Changhwan Lee ,  Taemin Eom ,  Seungmin Lee

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a first structure including a substrate, circuit devices, a lower interconnection structure electrically connected to the circuit devices, and a second structure on the first structure. The second structure includes a conductive plate layer; gate electrodes on the conductive plate layer and extending in a first direction; separation regions penetrating through the gate electrodes and extending in the first direction; channel structures penetrating through the gate electrodes and respectively including a channel layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction to be electrically connected to the lower interconnection structure of the first structure; first and second contacts electrically connected to the channel layer and the through-contact plugs, respectively; bitlines electrically connecting at least one of each of the first and second contacts to each other; and dummy contacts connected to the bitlines and spaced apart from the through-contact plugs.