公开(公告)号：US09627273B2

公开(公告)日：2017-04-18

申请号：US14964151

申请日：2015-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Su Kim

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823857 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

公开(公告)号：US09515147B2

公开(公告)日：2016-12-06

申请号：US15075888

申请日：2016-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil Yang ,  Sang-Su Kim ,  Sung-Gi Hur

IPC: H01L21/00 ,  H01L29/267 ,  H01L29/06 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L21/02233 ,  H01L21/823412 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0642 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.

公开(公告)号：US10074717B2

公开(公告)日：2018-09-11

申请号：US14993212

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0657 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US09391134B2

公开(公告)日：2016-07-12

申请号：US14336084

申请日：2014-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Jae Yang ,  Sang-Su Kim ,  Jae-Hwan Lee ,  Jung-Dal Choi

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/06 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract translation: 翅片场效应晶体管包括分别从第一和第二鳍结构上的衬底，第一和第二栅电极突出的第一鳍结构和第二鳍结构，以及在第一鳍和第二鳍结构中的每一个之间的栅极介电层 以及第一和第二栅电极。 第一和第二鳍结构中的每一个包括衬底上的缓冲图案，缓冲图案上的沟道图案，以及设置在沟道图案和衬底之间的蚀刻停止图案。 蚀刻停止图案包括具有大于缓冲图案的蚀刻电阻率的蚀刻电阻率的材料。

公开(公告)号：US09236435B2

公开(公告)日：2016-01-12

申请号：US14563155

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Xin-Gui Zhang ,  Tae-Yong Kwon ,  Sang-Su Kim

IPC: H01L29/78 ,  H01L29/205 ,  H01L29/165 ,  H01L29/73 ,  H01L29/737 ,  H01L29/739

CPC classification number: H01L29/205 ,  H01L29/165 ,  H01L29/7311 ,  H01L29/737 ,  H01L29/7376 ,  H01L29/7391 ,  H01L29/7848

Abstract: Tunneling field effect transistors are provided. The tunneling field effect transistor includes a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a first region adjacent to the source region and a second region adjacent to the drain region. A first energy band gap of the first region is lower than a second energy band gap of the second region, and the first region has a direct energy band gap.

Abstract translation: 提供隧道场效应晶体管。 隧道场效应晶体管包括源极区，漏极区和设置在源极区和漏极区之间的沟道区。 沟道区域包括与源极区域相邻的第一区域和与漏极区域相邻的第二区域。 第一区域的第一能带隙低于第二区域的第二能带隙，并且第一区域具有直接能带隙。

公开(公告)号：US09129815B2

公开(公告)日：2015-09-08

申请号：US14155192

申请日：2014-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gil Yang ,  Sang-Su Kim ,  Chang-Jae Yang

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/78

CPC classification number: H01L29/04 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848

Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.

Abstract translation: 本发明提供一种半导体器件，包括：包括第一区域和第二区域的衬底，分别依次层叠在第一区域上并具有第一至第三晶格常数的第一至第三晶体层，形成在第三晶体层上的第一栅电极，第四晶体管 和分别依次层叠在第二区域上并具有第四和第五晶格常数的第五晶体层和形成在第五晶体层上的第二栅电极，其中第三晶格常数大于第二晶格常数，第二晶格常数为 大于第一晶格常数，第五晶格常数小于第四晶格常数。