公开(公告)号：US11963362B2

公开(公告)日：2024-04-16

申请号：US17202992

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghun Jeong ,  Byoungil Lee ,  Bosuk Kang ,  Joonhee Lee

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other. The semiconductor device has a through-wiring region including a through-contact plug electrically connecting the memory cell structure and the peripheral circuit structure, the separation regions include first separation regions adjacent to the through-contact plug, and the first separation regions penetrate through the second horizontal conductive layer and are spaced apart from the first horizontal conductive layer.

公开(公告)号：US11356106B2

公开(公告)日：2022-06-07

申请号：US17334077

申请日：2021-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinwoong Kim ,  Myounggyun Kim ,  Joonhee Lee ,  Sangwook Han

IPC: H03L7/099 ,  H03L7/093 ,  H03D3/24

Abstract: An electronic device includes a phase locked loop configured to perform a two-point modulation operation on a data signal by using first and second modulation paths, and the phase locked loop is configured to generate, based on a differential value of a first phase error signal generated in the first modulation path, a gain for adjusting a frequency variation of the data signal through the second modulation path so as to match with the frequency variation of the data signal through the first modulation path.

公开(公告)号：US20220037347A1

公开(公告)日：2022-02-03

申请号：US17501149

申请日：2021-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11565 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US20190035806A1

公开(公告)日：2019-01-31

申请号：US15955256

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseong Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US09948301B2

公开(公告)日：2018-04-17

申请号：US15211459

申请日：2016-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook Han ,  Thomas Byunghak Cho ,  Jaehyun Lim ,  Sung-Jun Lee ,  Joonhee Lee ,  Jongwon Choi

IPC: H03L5/00 ,  H03K19/0175 ,  H01L27/02

CPC classification number: H03K19/017509 ,  H01L27/0248

Abstract: An integrated circuit (IC), a method of testing the IC, and a method of manufacturing the IC are provided. The IC includes analog circuitry, digital circuitry, at least one first connector, and a switching unit operatively coupled with the at least one first connector and configured to, if a first signal is received, couple the analog circuitry and the at least one first connector, and, if a second signal is received, couple the digital circuitry and the at least one first connector.

公开(公告)号：US12268006B2

公开(公告)日：2025-04-01

申请号：US17829011

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bosuk Kang ,  Joonhee Lee ,  Seonghun Jeong

IPC: H01L27/11575 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and extend in a second direction, and have different lengths on the second region, channel structures that penetrate the gate electrodes, extend in the first direction, and respectively include a channel layer on the first region, support structures that penetrate the gate electrodes and extend in the first direction on the second region, and a separation region that penetrates the gate electrodes and extend in the second direction. The substrate has a recess region that overlaps the separation region in the first direction and extends downward from an upper surface in the second region, adjacent to the first region. The separation region has a protrusion that protrudes downward to correspond to the recess region.

公开(公告)号：US11792982B2

公开(公告)日：2023-10-17

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Hojun Seong ,  Joonhee Lee ,  Joon-Sung Lim ,  Euntaek Jung

IPC: H01L27/11582 ,  H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US11621276B2

公开(公告)日：2023-04-04

申请号：US17035970

申请日：2020-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hun Jeong ,  Byoungil Lee ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

公开(公告)号：US20200335520A1

公开(公告)日：2020-10-22

申请号：US16921185

申请日：2020-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11575

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

公开(公告)号：US20180315772A1

公开(公告)日：2018-11-01

申请号：US16019119

申请日：2018-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

IPC: H01L27/11582 ,  H01L23/535 ,  H01L29/423 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42344

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.