公开(公告)号：US12268006B2

公开(公告)日：2025-04-01

申请号：US17829011

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bosuk Kang ,  Joonhee Lee ,  Seonghun Jeong

IPC: H01L27/11575 ,  H10B41/27 ,  H10B41/50 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor device includes a substrate having a first region and a second region, gate electrodes spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and extend in a second direction, and have different lengths on the second region, channel structures that penetrate the gate electrodes, extend in the first direction, and respectively include a channel layer on the first region, support structures that penetrate the gate electrodes and extend in the first direction on the second region, and a separation region that penetrates the gate electrodes and extend in the second direction. The substrate has a recess region that overlaps the separation region in the first direction and extends downward from an upper surface in the second region, adjacent to the first region. The separation region has a protrusion that protrudes downward to correspond to the recess region.

公开(公告)号：US11910600B2

公开(公告)日：2024-02-20

申请号：US17037532

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghun Jeong ,  Byoungil Lee ,  Bosuk Kang

IPC: H10B43/27 ,  H01L23/532 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5283 ,  H01L23/535 ,  H01L23/53257 ,  H01L23/53271 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A three-dimensional nonvolatile memory device includes: a substrate including a cell area and an extension area having a staircase structure; a vertical structure on the substrate; a stacking structure having electrode layers and interlayer insulating layers on the substrate; a separation insulating layer on the substrate and separating the electrode layers; and a through-via wiring area adjacent to the cell or extension area and having through-vias passing through the substrate, wherein the cell area includes a main cell area in which normal cells are arranged and an edge cell area, the separation insulating layer includes a main separation insulating layer in the main cell area and an edge separation insulating layer in the edge cell area, and a lower surface of the main separation insulating layer is higher than the upper surface of the substrate and has a different depth than a lower surface of the edge separation insulating layer.

公开(公告)号：US20240215253A1

公开(公告)日：2024-06-27

申请号：US18601027

申请日：2024-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghun Jeong ,  Byoungil Lee ,  Bosuk Kang ,  Joonhee Lee

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other. The semiconductor device has a through-wiring region including a through-contact plug electrically connecting the memory cell structure and the peripheral circuit structure, the separation regions include first separation regions adjacent to the through-contact plug, and the first separation regions penetrate through the second horizontal conductive layer and are spaced apart from the first horizontal conductive layer.

公开(公告)号：US11963362B2

公开(公告)日：2024-04-16

申请号：US17202992

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghun Jeong ,  Byoungil Lee ,  Bosuk Kang ,  Joonhee Lee

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/50 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit structure including a first substrate and circuit elements on the first substrate; and a memory cell structure including a second substrate on the first substrate, a first horizontal conductive layer on the second substrate, a second horizontal conductive layer on the first horizontal conductive layer, gate electrodes spaced apart from each other and stacked on the second horizontal conductive layer, channel structures penetrating through the gate electrodes, and separation regions penetrating the gate electrodes, extending, and spaced apart from each other. The semiconductor device has a through-wiring region including a through-contact plug electrically connecting the memory cell structure and the peripheral circuit structure, the separation regions include first separation regions adjacent to the through-contact plug, and the first separation regions penetrate through the second horizontal conductive layer and are spaced apart from the first horizontal conductive layer.