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    SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION 审中-公开

    公开(公告)号：US20230328990A1

    公开(公告)日：2023-10-12

    申请号：US18333886

    申请日：2023-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangjae Lee ,  Jaehyung Kim ,  Dongseog Eun

    IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

    CPC classification number: H10B43/27 ,  H10B43/40 ,  H10B43/35

    Abstract: A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

    SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES HAVING STACKED STRUCTURES THEREIN THAT SUPPORT HIGH INTEGRATION 有权

    公开(公告)号：US20210242235A1

    公开(公告)日：2021-08-05

    申请号：US16985024

    申请日：2020-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sangjae Lee ,  Jaehyung Kim ,  Dongseog Eun

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

    Abstract: A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

    Nonvolatile memory device and an erasing method thereof
    7.
    发明授权
    Nonvolatile memory device and an erasing method thereof 有权
    非易失性存储器件及其擦除方法

    公开(公告)号：US09558834B2

    公开(公告)日：2017-01-31

    申请号：US14887454

    申请日：2015-10-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byeong-In Choe ,  Mincheol Park ,  Dongseog Eun ,  Eunsuk Cho

    IPC: G11C16/04 ,  G11C16/14 ,  G11C7/04 ,  G11C16/32

    CPC classification number: G11C16/14 ,  G11C7/04 ,  G11C16/32

    Abstract: An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.

    Abstract translation: 非易失性存储器件的擦除方法包括向衬底施加擦除电压; 感测存储单元阵列的温度; 基于所述存储单元阵列的温度来设置延迟时间，其中所述延迟时间响应于所述擦除电压被施加到所述衬底而开始; 在延迟时间内将接地电压施加到接地选择晶体管的接地选择线; 并在延迟时间后增加接地选择线的电压。

    SEMICONDUCTOR DEVICES
    9.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220037347A1

    公开(公告)日：2022-02-03

    申请号：US17501149

    申请日：2021-10-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwangyoung Jung ,  Jongwon Kim ,  Dongseog Eun ,  Joonhee Lee

    IPC: H01L27/11565 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.

    Three dimensional semiconductor memory devices
    10.
    发明授权
    Three dimensional semiconductor memory devices 有权

    公开(公告)号：US10971518B2

    公开(公告)日：2021-04-06

    申请号：US16411638

    申请日：2019-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jibong Park ,  Soyeon Kim ,  Hanyoung Lee ,  Young-Bae Yoon ,  Dongseog Eun

    IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

    Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including electrodes vertically stacked on the substrate and each having a pad portion, electrode separation structures penetrating the electrode structure and apart from each other in a second direction, and contact plugs coupled to the pad portions. The contact plugs comprise first contact plugs and second contact plugs apart in the second direction from the first contact plugs. The electrode separation structures comprise a first electrode separation between the first and second contact plugs. The first contact plugs are apart in the second direction at a first distance from the first electrode separation structure. The second contact plugs are apart in the second direction from the first electrode separation structure at a second distance, different from the first distance.

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