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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220328520A1

    公开(公告)日：2022-10-13

    申请号：US17851310

    申请日：2022-06-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

    Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200227438A1

    公开(公告)日：2020-07-16

    申请号：US16837169

    申请日：2020-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang-Sup Lee ,  Sung-Hun Lee ,  Joonhee Lee ,  Seong Soon Cho

    IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L29/423

    Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

    Semiconductor devices including a gate electrode and methods of manufacturing the same
    10.
    发明授权
    Semiconductor devices including a gate electrode and methods of manufacturing the same 有权
    包括栅电极的半导体器件及其制造方法

    公开(公告)号：US09508732B2

    公开(公告)日：2016-11-29

    申请号：US14746205

    申请日：2015-06-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Hun Lee ,  Ki-Yong Kim ,  Sung-Wook Park ,  Gyu-Yeol Lee

    IPC: H01L27/115 ,  H01L29/49 ,  H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234

    CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L21/823437 ,  H01L21/823443 ,  H01L21/823456 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/495 ,  H01L29/4975 ,  H01L29/788

    Abstract: In a semiconductor device, a first gate structure is provided in a cell transistor region and includes a floating gate electrode, a first dielectric layer pattern, and a control gate electrode including a first metal silicide pattern. A second gate structure is provided in a selecting transistor region and includes a first conductive layer pattern, a second dielectric layer pattern, and a first gate electrode including a second metal silicide pattern. A third gate structure is provided in a peripheral circuit region and includes a second conductive layer pattern, a third dielectric layer pattern including opening portions on the second conductive layer pattern, and a second gate electrode including a concavo-convex portion at an upper surface portion thereof and a third metal silicide pattern. The third metal silicide pattern has a uniform thickness.

    Abstract translation: 在半导体器件中，第一栅极结构设置在单元晶体管区域中，并且包括浮置栅电极，第一介电层图案和包括第一金属硅化物图案的控制栅电极。 第二栅极结构设置在选择晶体管区域中，并且包括第一导电层图案，第二介电层图案和包括第二金属硅化物图案的第一栅电极。 第三栅极结构设置在外围电路区域中，并且包括第二导电层图案，在第二导电层图案上包括开口部分的第三介电层图案，以及在上表面部分包括凹凸部分的第二栅电极 和第三金属硅化物图案。 第三金属硅化物图案具有均匀的厚度。

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