公开(公告)号：US20240079280A1

公开(公告)日：2024-03-07

申请号：US18322714

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Hyung Kim ,  Ji Young Kim ,  Ji Won Kim ,  Suk Kang Sung ,  Woo Sung Yang

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

公开(公告)号：US20230292521A1

公开(公告)日：2023-09-14

申请号：US18153763

申请日：2023-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Yong JEON ,  Eun-Ji Kim ,  Ji Young Kim ,  Moo Rym Choi

IPC: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B43/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit and a first bonding pad, the first bonding pad connected to the peripheral circuit, a cell structure on the peripheral circuit structure, the cell structure including a second bonding pad bonded to the first bonding pad, and a pad structure on the cell structure. The cell structure includes a cell substrate having a first face, a second face opposite to the first face, a first contact plug extending through the cell substrate and connected to an electrode layer, and a second contact plug extending through the cell substrate and connected to the cell substrate. Each of the first contact plug and the second contact plug is connected to the pad structure, and a bypass via is in contact with the pad structure on the second face.

公开(公告)号：US11462547B2

公开(公告)日：2022-10-04

申请号：US16991738

申请日：2020-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin A Kim ,  Sun Young Lee ,  Yong Kwan Kim ,  Ji Young Kim ,  Chang Hyun Cho

IPC: H01L27/108 ,  H01L21/66

Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

公开(公告)号：US20200227314A1

公开(公告)日：2020-07-16

申请号：US16545150

申请日：2019-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong Gil Kim ,  Han Seong Kim ,  Jong Min Baek ,  Ji Young Kim ,  Sung Bin Park ,  Deok Young Jung ,  Kyu Hee Han

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.

公开(公告)号：US10708777B2

公开(公告)日：2020-07-07

申请号：US15783451

申请日：2017-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakjoo Kim ,  Yong-Jun Park ,  Gwiho Lee ,  Ho-Dong Jwa ,  Ji Young Kim ,  Sangho Park ,  Hyunseung Lee ,  Wooyoung Choi

IPC: G06F21/00 ,  H04W12/06 ,  H04W12/10 ,  H04L29/06 ,  G06F21/33 ,  G06F21/30 ,  G06F21/34 ,  G06F21/45 ,  H04W12/04 ,  H04W12/08

Abstract: Disclosed are a method and an apparatus for connecting electronic devices based on biometric information without a certification server. An electronic device includes a wireless communication unit configured to perform wireless communication with an external device; a biometric recognition module; a memory; and a processor connected to the wireless communication unit, the biometric recognition module, and the memory. The processor is configured to register, in the external device, authentication information for authenticating the external device through the electronic device, establish a communication connection with the external device through the wireless communication unit, receive a request for authenticating the electronic device from the external device in response to the communication connection, acquire biometric information corresponding to a user of the electronic device using the biometric recognition module in response to the authentication request, perform device authentication for the user based on at least the biometric information, encrypt authentication information when the authentication is successfully performed, and transmit the encrypted authentication information to the external device.

公开(公告)号：US10201437B2

公开(公告)日：2019-02-12

申请号：US14558081

申请日：2014-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Young Kim ,  Kyung-Won Moon ,  Young Bo Shim ,  Ju Suk Lee

IPC: A61F2/68 ,  A61F2/70 ,  A61F2/72 ,  A61H3/00 ,  A61H1/02

Abstract: Disclosed herein is a control method of a wearable robot, including: generating reference gait data based on the results of sensing by a sensor unit included in a structure; estimating, when a wearer walks, the wearer's gait phase based on the results of sensing by the sensor unit; detecting a gait phase having a minimum difference from the estimated gait phase from the reference gait data; and driving a driver of the structure, according to a control signal generated based on the estimated gait phase and the detected gait phase.

公开(公告)号：US20250071992A1

公开(公告)日：2025-02-27

申请号：US18604586

申请日：2024-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Yong Lee ,  Se Hoon Lee ,  Jun Hyoung Kim ,  Ji Young Kim ,  Suk Kang Sung

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor memory device may include a cell substrate including a first surface and a second surface opposite to the first surface, and a landing pattern including a third surface and a fourth surface opposite to the third surface, with the landing pattern spaced apart from the cell substrate in a horizontal direction. The semiconductor memory device may include a plurality of gate electrodes sequentially stacked on the first surface and the third surface, a channel structure on the cell substrate, the channel structure extending vertically and intersecting the plurality of gate electrodes, an upper insulating film covering the second surface and the fourth surface, an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction, and a support contact extending through the upper insulating film and connecting the landing pattern and the input/output pad.

公开(公告)号：US12144167B2

公开(公告)日：2024-11-12

申请号：US17821331

申请日：2022-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin A Kim ,  Sun Young Lee ,  Yong Kwan Kim ,  Ji Young Kim ,  Chang Hyun Cho

IPC: H10B12/00 ,  H01L21/66

Abstract: A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.

公开(公告)号：US20230403854A1

公开(公告)日：2023-12-14

申请号：US18180437

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Young Kim ,  Do Hyung Kim ,  Ji Won Kim ,  Suk Kang Sung

IPC: H10B43/27 ,  H10B80/00

CPC classification number: H10B43/27 ,  H10B80/00

Abstract: According to some implementations of the present disclosure, a semiconductor memory device includes a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including: a plate disposed on the second face of the semiconductor layer; and a plug extending from the plate through the semiconductor layer; a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one an other; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.

公开(公告)号：US11282833B2

公开(公告)日：2022-03-22

申请号：US16660976

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Jin Lee ,  Ji Young Kim ,  Bong Soo Kim ,  Hyeon Kyun Noh ,  Moon Young Jeong

IPC: H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/22

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.