公开(公告)号：US11201168B2

公开(公告)日：2021-12-14

申请号：US16735085

申请日：2020-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lee Eun Ku ,  Jae Ho Jeong ,  Woo Sung Yang ,  Jung Hwan Lee ,  In Su Noh ,  Sun Young Lee

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device includes a structure including gate electrodes and interlayer insulating layers alternately stacked on an upper surface of a substrate, trenches passing through the structure; and a groove passing through a portion of the structure. The gate electrodes include word lines, and first and second select lines. The word lines are stacked in a vertical direction upwardly from the upper surface of the substrate. The first and second select lines are on the word lines, and are spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate. The trenches include a first trench and a second trench spaced apart from the first trench. The groove is on the word lines. The groove and a portion of the first trench are between the first select line and the second select line. The second trench is spaced apart from the select lines.

公开(公告)号：US11956957B2

公开(公告)日：2024-04-09

申请号：US17203122

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Young Kim ,  Woo Sung Yang ,  Sung-Min Hwang ,  Suk Kang Sung ,  Joon-Sung Lim

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.

公开(公告)号：US10529734B2

公开(公告)日：2020-01-07

申请号：US15869766

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lee Eun Ku ,  Jae Ho Jeong ,  Woo Sung Yang ,  Jung Hwan Lee ,  In Su Noh ,  Sun Young Lee

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11582

Abstract: A semiconductor device can include a semiconductor substrate having a memory cell region and a pad region that is adjacent to the memory cell region, the pad region can include a first pad region, a second pad region between the memory cell region and the first pad region, and a buffer region that is between the first and second pad regions. A separation source structure can include a first portion and a second portion that are parallel to each other in a plan view of the semiconductor device. A first source structure and a second source structure can be disposed between the first and second portions of the separation source structure, where the first and second source structures can have end portions that oppose each other, the first source structure being disposed in the first pad region, and the second source structure being disposed in the second pad region. A gate group can be disposed in the memory cell region and the pad region between the first and second portions of the separation source structure, where each of the end portions of the first and second source structures has a planar shape, and a width of each end portion increases and then decreases as each of the end portions extends toward the other.

公开(公告)号：US20240079280A1

公开(公告)日：2024-03-07

申请号：US18322714

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Hyung Kim ,  Ji Young Kim ,  Ji Won Kim ,  Suk Kang Sung ,  Woo Sung Yang

IPC: H01L21/66

CPC classification number: H01L22/34

Abstract: There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.

公开(公告)号：US20200227435A1

公开(公告)日：2020-07-16

申请号：US16686967

申请日：2019-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Hwang ,  Joon Sung Lim ,  Woo Sung Yang ,  Dong Sik Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.

公开(公告)号：US11910611B2

公开(公告)日：2024-02-20

申请号：US17507989

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hoon Jang ,  Woo Sung Yang ,  Joon Sung Lim ,  Sung Min Hwang

IPC: H10B43/40 ,  H01L23/522 ,  H10B43/27 ,  H10B43/10

CPC classification number: H10B43/40 ,  H01L23/5226 ,  H10B43/10 ,  H10B43/27

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

公开(公告)号：US11139314B2

公开(公告)日：2021-10-05

申请号：US16686967

申请日：2019-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Hwang ,  Joon Sung Lim ,  Woo Sung Yang ,  Dong Sik Lee

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes gate electrodes spaced apart from each other in a first direction perpendicular to a substrate's upper surface, and extending by different lengths in a second direction perpendicular to the first direction. The device further includes first and second channels penetrating the gate electrodes and extending in the first direction, a horizontal portion disposed in lower portions of the gate electrodes and connecting lower portions of the first and second channels to each other, and a source line disposed in an upper portion of the second channel and connected to the second channel. The gate electrodes include memory cell electrodes included in memory cells, a first ground select electrode disposed in lower portions of the memory cell electrodes, a second ground select electrode disposed in upper portions of the memory cell electrodes, and a string select electrode disposed in upper portions of the memory cell electrodes.