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    Method of fabricating a semiconductor memory device including an extension gate cutting region
    3.
    发明授权
    Method of fabricating a semiconductor memory device including an extension gate cutting region 有权

    公开(公告)号：US12218062B2

    公开(公告)日：2025-02-04

    申请号：US18514716

    申请日：2023-11-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim ,  Young-Jin Kwon ,  Geun Won Lim

    IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

    Semiconductor memory device and method of manufacturing the same
    4.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权

    公开(公告)号：US10797071B2

    公开(公告)日：2020-10-06

    申请号：US16251337

    申请日：2019-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim ,  Kwang Soo Kim ,  Geun Won Lim

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565 ,  H01L21/28

    Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

    Vertical memory devices
    7.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US10861877B2

    公开(公告)日：2020-12-08

    申请号：US16927280

    申请日：2020-07-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim

    IPC: H01L27/11582 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/522

    Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.

    VERTICAL MEMORY DEVICES
    8.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20190333932A1

    公开(公告)日：2019-10-31

    申请号：US16235122

    申请日：2018-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun Hyoung Kim

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/522 ,  H01L21/768

    Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.

    Three-dimensional semiconductor memory device
    9.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10991714B2

    公开(公告)日：2021-04-27

    申请号：US16223761

    申请日：2018-12-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwang Soo Kim ,  Jun Hyoung Kim ,  Si Wan Kim ,  Kyoung Taek Oh

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/423 ,  H01L27/11573 ,  G11C16/08

    Abstract: A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.

    Vertical memory devices
    10.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US10748924B2

    公开(公告)日：2020-08-18

    申请号：US16235122

    申请日：2018-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Hyoung Kim

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L21/768 ,  H01L23/522 ,  H01L27/11565

    Abstract: A vertical memory device includes first gate electrodes spaced apart from each other under a substrate in a first direction substantially perpendicular to a lower surface of the substrate, the first gate electrodes being arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the lower surface of the substrate gradually increase from an uppermost level toward a lowermost level, second gate electrodes spaced apart from each other under the first gate electrodes in the first direction, the second gate electrodes being arranged to have a staircase shape including steps of which extension lengths in the second direction gradually decrease from an uppermost level toward a lowermost level and a channel extending through the first and second gate electrodes in the first direction.

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