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公开(公告)号：US11956957B2
公开(公告)日：2024-04-09
申请号：US17203122
申请日：2021-03-16
发明人： Ji Young Kim , Woo Sung Yang , Sung-Min Hwang , Suk Kang Sung , Joon-Sung Lim
摘要： A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack.
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公开(公告)号：US10825766B2
公开(公告)日：2020-11-03
申请号：US16285583
申请日：2019-02-26
发明人： Ji Young Kim , Kyu Hee Han , Sung Bin Park , Yeong Gil Kim , Jong Min Baek , Kyoung Woo Lee , Deok Young Jung
IPC分类号： H01L23/522 , H01L23/528 , H01L23/532 , H01L21/768 , H01L21/311
摘要： A semiconductor device includes a lower wiring, an interlayer insulation film above the lower wiring and including a first portion having a first density, and a second portion on the first portion, the first portion and the second portion having a same material, and the second portion having a second density smaller than the first density, an upper wiring in the second portion of the interlayer insulating film, and a via in the first portion of the interlayer insulating film, the via connecting the upper wiring and the lower wiring.
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公开(公告)号：US20180175040A1
公开(公告)日：2018-06-21
申请号：US15722085
申请日：2017-10-02
发明人： JIN A KIM , Sun Young Lee , Ji Young Kim , Chang Hyun Cho
IPC分类号： H01L27/108 , H01L29/423 , H01L21/762
CPC分类号： H01L27/10829 , H01L21/76224 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/1087 , H01L27/10876 , H01L29/4236
摘要： A semiconductor device is provided. The provided semiconductor device may have enhanced reliability and operating characteristics. The semiconductor device includes a substrate, a device isolation film formed within the substrate, a first gate structure formed within the substrate, a recess formed on at least one side of the first gate structure and within the substrate and the device isolation film, the recess comprising an upper portion and a lower portion wherein the lower portion of the recess is formed within the substrate and the upper portion of the recess is formed across the substrate and the device isolation film, a buried contact filling the recess and an information storage electrically connected to the buried contact.
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公开(公告)号：US20240079280A1
公开(公告)日：2024-03-07
申请号：US18322714
申请日：2023-05-24
发明人： Do Hyung Kim , Ji Young Kim , Ji Won Kim , Suk Kang Sung , Woo Sung Yang
IPC分类号： H01L21/66
CPC分类号： H01L22/34
摘要： There is provided a nonvolatile memory device having improved crack detection reliability. The nonvolatile memory device comprises word lines that extend in a first direction, cell contact plugs that are electrically connected to the word lines and extend in a second direction intersecting the first direction, a net crack detection circuit that is on the word lines and is not in contact with the word lines, and a ring crack detection circuit that is on the word lines and is not in contact with the word lines, wherein the net crack detection circuit is electrically connected to a crack detection transistor in a peripheral circuit region, the ring crack detection circuit includes a first crack detection metal wiring that extends in a third direction intersecting the first direction and the second direction, and a second crack detection metal wiring that extends in the third direction.
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公开(公告)号：US20230292521A1
公开(公告)日：2023-09-14
申请号：US18153763
申请日：2023-01-12
发明人： Woo Yong JEON , Eun-Ji Kim , Ji Young Kim , Moo Rym Choi
IPC分类号： H10B43/40 , H10B43/10 , H10B43/27 , H10B43/35 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
CPC分类号： H10B43/40 , H10B43/10 , H10B43/27 , H10B43/35 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40
摘要： A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit and a first bonding pad, the first bonding pad connected to the peripheral circuit, a cell structure on the peripheral circuit structure, the cell structure including a second bonding pad bonded to the first bonding pad, and a pad structure on the cell structure. The cell structure includes a cell substrate having a first face, a second face opposite to the first face, a first contact plug extending through the cell substrate and connected to an electrode layer, and a second contact plug extending through the cell substrate and connected to the cell substrate. Each of the first contact plug and the second contact plug is connected to the pad structure, and a bypass via is in contact with the pad structure on the second face.
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公开(公告)号：US11462547B2
公开(公告)日：2022-10-04
申请号：US16991738
申请日：2020-08-12
发明人： Jin A Kim , Sun Young Lee , Yong Kwan Kim , Ji Young Kim , Chang Hyun Cho
IPC分类号： H01L27/108 , H01L21/66
摘要： A method of fabricating a semiconductor device. A cell area and a core area is defined in a substrate. A bit line structure disposed in the cell area is provided. A gate structure disposed in the core area is provided, and a core capping film disposed on the gate structure is provided. A height of the core capping film is greater than a height of the bit line structure. A first contact film is formed on the bit line structure. A second contact film is formed on the core capping film. A mask is formed on the first contact film. An upper surface of the core capping film is exposed using the mask. The first contact film is etched until a height of the first contact film becomes less than a height of the bit line structure using an etching process. In the etching process, an etching rate for the first contact film is greater than etching rates for the bit line structure and the core capping film.
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公开(公告)号：US20200227314A1
公开(公告)日：2020-07-16
申请号：US16545150
申请日：2019-08-20
发明人： Yeong Gil Kim , Han Seong Kim , Jong Min Baek , Ji Young Kim , Sung Bin Park , Deok Young Jung , Kyu Hee Han
IPC分类号： H01L21/768 , H01L21/02 , H01L21/311
摘要： A method of fabricating a semiconductor device is provided. The method may include forming a first interlayer insulating film on a substrate, forming a second interlayer insulating film on the first interlayer insulating film, and forming a third interlayer insulating film on the second interlayer insulating film. Different amounts of carbon may be present in each of the first, second, and third interlayer insulating films. The third interlayer insulating film may be used as a mask pattern to form a via trench that extends at least partially into the first interlayer insulating film and the second interlayer insulating film. Supplying a carbon precursor may be interrupted between the forming of the second and third interlayer insulating films, such that the second interlayer insulating film and the third interlayer insulating film may have a discontinuous boundary therebetween.
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公开(公告)号：US10708777B2
公开(公告)日：2020-07-07
申请号：US15783451
申请日：2017-10-13
发明人： Hakjoo Kim , Yong-Jun Park , Gwiho Lee , Ho-Dong Jwa , Ji Young Kim , Sangho Park , Hyunseung Lee , Wooyoung Choi
IPC分类号： G06F21/00 , H04W12/06 , H04W12/10 , H04L29/06 , G06F21/33 , G06F21/30 , G06F21/34 , G06F21/45 , H04W12/04 , H04W12/08
摘要： Disclosed are a method and an apparatus for connecting electronic devices based on biometric information without a certification server. An electronic device includes a wireless communication unit configured to perform wireless communication with an external device; a biometric recognition module; a memory; and a processor connected to the wireless communication unit, the biometric recognition module, and the memory. The processor is configured to register, in the external device, authentication information for authenticating the external device through the electronic device, establish a communication connection with the external device through the wireless communication unit, receive a request for authenticating the electronic device from the external device in response to the communication connection, acquire biometric information corresponding to a user of the electronic device using the biometric recognition module in response to the authentication request, perform device authentication for the user based on at least the biometric information, encrypt authentication information when the authentication is successfully performed, and transmit the encrypted authentication information to the external device.
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公开(公告)号：US10201437B2
公开(公告)日：2019-02-12
申请号：US14558081
申请日：2014-12-02
发明人： Ji Young Kim , Kyung-Won Moon , Young Bo Shim , Ju Suk Lee
摘要： Disclosed herein is a control method of a wearable robot, including: generating reference gait data based on the results of sensing by a sensor unit included in a structure; estimating, when a wearer walks, the wearer's gait phase based on the results of sensing by the sensor unit; detecting a gait phase having a minimum difference from the estimated gait phase from the reference gait data; and driving a driver of the structure, according to a control signal generated based on the estimated gait phase and the detected gait phase.
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公开(公告)号：US20230403854A1
公开(公告)日：2023-12-14
申请号：US18180437
申请日：2023-03-08
发明人： Ji Young Kim , Do Hyung Kim , Ji Won Kim , Suk Kang Sung
摘要： According to some implementations of the present disclosure, a semiconductor memory device includes a semiconductor layer including a first face and a second face opposite to the first face in a first direction directed upward from the first face to the second face; a source structure including: a plate disposed on the second face of the semiconductor layer; and a plug extending from the plate through the semiconductor layer; a plurality of gate electrodes disposed on the first face of the semiconductor layer and sequentially stacked on one an other; and a channel structure that extends through the plurality of gate electrodes and that is disposed on the plug, wherein the channel structure is electrically connected to the source structure.
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