公开(公告)号：US09287357B2

公开(公告)日：2016-03-15

申请号：US14737048

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna Obradovic ,  Rwik Sengupta ,  Dharmendar Reddy Palle ,  Robert C. Bowen

IPC: H01L29/06 ,  H01L29/20 ,  H01L27/092 ,  B82Y10/00

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/755

Abstract: An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs.

Abstract translation: 集成电路可以包括多个第一，非Si，纳米片状场效应晶体管（FET）和多个第二，Si，纳米片FET。 第一非硅纳米片FET的纳米片可以包括少于约30％的Si。 第一个非Si纳米片FET可以限定集成电路的电路的临界速度路径。 第二，Si，纳米片FET的纳米片可以包括大于约30％的Si。 第二个Si纳米片FET可以定义集成电路的非临界速度路径。 第一非硅纳米片FET的结构可以被配置为具有比第二Si纳米片FET的速度更高的速度。

公开(公告)号：US10181527B2

公开(公告)日：2019-01-15

申请号：US15169621

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Borna Obradovic ,  Joon Goo Hong ,  Mark Rodder

IPC: H01L29/78 ,  H01L29/66

Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.

公开(公告)号：US09905672B2

公开(公告)日：2018-02-27

申请号：US15276784

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Borna J. Obradovic ,  Dharmendar Reddy Palle ,  Joon Goo Hong

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/04

CPC classification number: H01L29/66553 ,  H01L21/02236 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0259 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78

Abstract: A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

公开(公告)号：US09773886B1

公开(公告)日：2017-09-26

申请号：US15340827

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/167

CPC classification number: H01L29/66553 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method of forming a horizontal nanosheet device or a horizontal nanowire device includes forming a dummy gate and a series of external spacers on a stack including an alternating arrangement of sacrificial layers and channel layers, deep etching portions of the stack between the external spacers to form electrode recesses for a source electrode and a drain electrode, performing an etch-back on portions of the sacrificial layers to form internal spacer recesses above and below each of the channel layers, forming doped internal spacers in the internal spacer recesses, and forming doped extension regions of the source electrode and the drain electrode by outdiffusion of dopants from the doped internal spacers. The method may also include epitaxially regrowing the source electrode and the drain electrode in the electrode recesses.

公开(公告)号：US20170110568A1

公开(公告)日：2017-04-20

申请号：US15169621

申请日：2016-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dharmendar Reddy Palle ,  Borna Obradovic ,  Joon Goo Hong ,  Mark Rodder

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.