公开(公告)号：US10446561B2

公开(公告)日：2019-10-15

申请号：US16115711

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US09984925B2

公开(公告)日：2018-05-29

申请号：US15182024

申请日：2016-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Ho Jeon ,  Sang-Su Kim ,  Cheol Kim ,  Yong-Suk Tak ,  Myung-Geun Song ,  Gi-Gwan Park

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.

公开(公告)号：US09806168B2

公开(公告)日：2017-10-31

申请号：US14988867

申请日：2016-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： GeumJung Seong ,  JinWook Lee ,  Dohyoung Kim ,  Sungwoo Myung ,  Jisoo Oh ,  Yong-Ho Jeon

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/31058 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/401 ,  H01L29/4966

Abstract: The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.

公开(公告)号：US09806166B2

公开(公告)日：2017-10-31

申请号：US15401562

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungwoo Myung ,  GeumJung Seong ,  Jisoo Oh ,  JinWook Lee ,  Dohyoung Kim ,  Yong-Ho Jeon

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.