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    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11581279B2

    公开(公告)日：2023-02-14

    申请号：US17229023

    申请日：2021-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

    IPC: H01L23/00

    Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

    Semiconductor devices including a through via structure and methods of forming the same
    12.
    发明授权
    Semiconductor devices including a through via structure and methods of forming the same 有权

    公开(公告)号：US10103098B2

    公开(公告)日：2018-10-16

    申请号：US15403480

    申请日：2017-01-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deokyoung Jung ,  Kwangjin Moon ,  Byung Lyul Park ,  Jin Ho An

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

    Abstract: Semiconductor devices including a through via structure and methods of forming the same are provided. The semiconductor devices may include a semiconductor substrate including a first surface and a second surface opposite the first surface, a front insulating layer on the first surface of the semiconductor substrate, a back insulating layer on the second surface of the semiconductor substrate, a through via structure extending through the back insulating layer, the semiconductor substrate, and the front insulating layer, a via insulating layer on a side surface of the through via structure, and a contact structure extending through the front insulating layer. The through via structure may include a first region and a second region disposed on the first region. The second region may include a first doping element, and the first region may be substantially free of the first doping element.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    15.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220037255A1

    公开(公告)日：2022-02-03

    申请号：US17210044

    申请日：2021-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

    IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/48

    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

    Semiconductor devices and methods of fabricating the same
    17.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US09076849B2

    公开(公告)日：2015-07-07

    申请号：US14094963

    申请日：2013-12-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin Ho An ,  Byung-Lyul Park ,  Soyoung Lee ,  Gilheyun Choi

    IPC: H01L21/44 ,  H01L21/768

    CPC classification number: H01L23/5384 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/08146 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

    Abstract: Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.

    Abstract translation: 半导体器件以及制造半导体器件的方法包括：通过基板的第一表面形成通孔，所述通孔与面向第一表面的第二表面间隔开，在通孔中形成第一导电图案，形成 在所述基板的第一表面上的绝缘垫层，所述绝缘垫具有暴露所述第一导电图案的开口，对所述第一导电图案进行热处理，以形成从所述第一导电图案的顶表面朝向所述开口突出的突起 ，然后在开口中形成第二导电图案。

    Semiconductor package
    19.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12183664B2

    公开(公告)日：2024-12-31

    申请号：US17381869

    申请日：2021-07-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-Il Choi ,  Gyuho Kang ,  Seong-Hoon Bae ,  Jin Ho An ,  Jeonggi Jin ,  Atsushi Fujisaki

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

    Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

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