公开(公告)号：US20130119454A1

公开(公告)日：2013-05-16

申请号：US13732235

申请日：2012-12-31

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Tsutomu Okazaki

IPC: H01L29/788

CPC classification number: H01L29/788 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

Abstract: A technique capable of improving the reliability of a non-volatile memory semiconductor device is provided and, in particular, a technique capable of supplying electricity without fail to a memory gate electrode of split gate transistor is provided.One end of an electricity supply line ESL is arranged over a terminal end TE1 and the other end thereof is arranged over a terminal end TE2, and further, the central portion of the electricity supply line ESL is arranged over a dummy part DMY. That is, the terminal end TE1, the terminal end TE2, and the dummy part DMY have substantially the same height, and therefore, most of the electricity supply line ESL arranged from over the terminal end TE1 to over the terminal end TE2 via the dummy part DMY is formed so as to have the same height.

Abstract translation: 提供了一种能够提高非易失性存储器半导体器件的可靠性的技术，特别地，提供了一种能够不经过电源分配给分离栅晶体管的存储栅电极的技术。 供电线ESL的一端设置在终端TE1的上端，其另一端配置在终端TE2的上方，而且供电线ESL的中心部分配置在虚拟部分DMY上。 也就是说，终端TE1，终端TE2和虚拟部分DMY具有基本上相同的高度，因此，从终端TE1的上方排列的电力供给线ESL大部分经由虚拟的终端TE2 部分DMY形成为具有相同的高度。

公开(公告)号：US20190326311A1

公开(公告)日：2019-10-24

申请号：US16374320

申请日：2019-04-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiraku CHAKIHARA

IPC: H01L27/11565 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L23/522 ,  H01L21/28 ,  H01L21/66 ,  H01L29/78

Abstract: There is provided a semiconductor device including a first gate pattern on a semiconductor substrate, a second gate pattern adjacent to a side surface of the first gate pattern via an ONO film, and an active region located just below the second gate pattern via the ONO film. Here, an element isolation region is formed just below the first gate pattern. In this manner, capacitance between the first gate pattern and the semiconductor substrate and capacitance between the first and second gate patterns are prevented from being measured when measuring capacitance between the second gate pattern which is an upper electrode and the active region which is a lower electrode in order to measure a film thickness of the ONO film just below the second gate pattern.

公开(公告)号：US20160225902A1

公开(公告)日：2016-08-04

申请号：US15093048

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Koichi TOBA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA ,  Kentaro SAITO ,  Takashi HASHIMOTO

IPC: H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7847 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3105 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/0922 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833

Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

公开(公告)号：US20140035027A1

公开(公告)日：2014-02-06

申请号：US13958574

申请日：2013-08-04

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/423 ,  H01L29/792

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract translation: 在半导体衬底上形成具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 与层压图案相邻地形成存储栅电极。 在控制栅极和半导体衬底之间形成栅极绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成第四绝缘膜，其包括氧化硅膜的叠层膜，氮化硅膜和另一氧化硅膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

公开(公告)号：US20130149854A1

公开(公告)日：2013-06-13

申请号：US13662509

申请日：2012-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasushi ISHII ,  Hiraku CHAKIHARA ,  Kentaro SAITO

IPC: H01L21/82

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract translation: 在包括在相同基板上具有不同特性的多个场效应晶体管的半导体器件的制造成品率方面的改进。 通过将各向异性干法蚀刻与各向同性湿蚀刻或各向同性干法蚀刻相结合，形成具有不同侧壁长度的三种类型的侧壁。 通过减少各向异性干蚀刻步骤的数量，在布置密度高的第三n型MISFET区域和第三p型MISFET区域中，可以防止半导体衬底在n型栅极之间被部分切割 彼此相邻的n型栅电极和彼此相邻的p型栅极之间，以及彼此相邻的p型栅电极。

公开(公告)号：US20230093724A1

公开(公告)日：2023-03-23

申请号：US17876067

申请日：2022-07-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi AMO ,  Hiraku CHAKIHARA ,  Hiroshi YANAGITA ,  Akio ONO

IPC: H01L21/66 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51

Abstract: A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.

公开(公告)号：US20180097008A1

公开(公告)日：2018-04-05

申请号：US15669814

申请日：2017-08-04

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro HAYASHI ,  Hiraku CHAKIHARA

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/785 ,  H01L29/792

Abstract: Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region surrounded by a first fin, a second fin, a memory gate electrode, and another memory gate electrode, a protruding portion is provided. In a second isolation region which is the element isolation region overlapping the memory gate electrode in plan view, a second isolation portion is provided to set the protruding portion higher in level than the second isolation portion. In a step of lowering a top surface of the element isolation region located between the first and second fins, a part of the element isolation region located between the first and second fins is covered with a mask film to form the protruding portion. Using the protruding portion, a short circuit between the memory gate electrodes due to a gate residue is prevented.

公开(公告)号：US20170053922A1

公开(公告)日：2017-02-23

申请号：US15236472

申请日：2016-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

Abstract translation: 在半导体器件中，存储单元由彼此相邻的控制栅电极和存储栅电极形成，形成在控制栅电极下方的栅绝缘膜和形成在存储栅电极下方并具有电荷累积的绝缘膜 其中的部分。 此外，在该半导体器件中，电容元件由形成在上电极和下电极之间的下电极，上电极和电容绝缘膜形成。 下电极的厚度小于控制栅电极的厚度。

公开(公告)号：US20160035739A1

公开(公告)日：2016-02-04

申请号：US14884273

申请日：2015-10-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kentaro SAITO ,  Hiraku CHAKIHARA

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L21/02 ,  H01L29/423 ,  H01L21/3213

CPC classification number: H01L27/11568 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/1157 ,  H01L29/0642 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side.

Abstract translation: 提高了半导体器件的性能。 半导体器件具有沿着栅极长度方向间隔开的第一控制栅电极和第二控制栅电极，形成在第一控制栅电极上的第一帽绝缘膜，以及形成在第二控制栅电极上的第二帽绝缘膜。 此外，半导体器件具有布置在与第二控制栅电极相对的第一控制栅极侧的第一存储栅极，以及布置在第二控制栅电极与第一控制栅相反的一侧的第二存储栅电极 栅电极。 第二控制栅电极侧的第一帽绝缘膜的顶面的端部比第二控制栅电极侧的第一控制栅电极的侧面更靠近第一存储栅电极侧。

公开(公告)号：US20130164927A1

公开(公告)日：2013-06-27

申请号：US13772470

申请日：2013-02-21

Applicant: Renesas Electronics Corporation

Inventor： Hiraku CHAKIHARA ,  Yasushi ISHII

IPC: H01L29/66

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract translation: 在半导体衬底上形成具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 与层压图案相邻地形成存储栅电极。 在控制栅极和半导体衬底之间形成栅极绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成第四绝缘膜，其包括氧化硅膜的叠层膜，氮化硅膜和另一氧化硅膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。