公开(公告)号：US10175571B2

公开(公告)日：2019-01-08

申请号：US15182510

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Hyeokjin Bruce Lim ,  Ohsang Kwon ,  Mickael Malabry ,  Jingwei Zhang ,  Raymond George Stephany ,  Haining Yang ,  Kern Rim ,  Stanley Seungchul Song ,  Mukul Gupta ,  Foua Vang

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

公开(公告)号：US20180076197A1

公开(公告)日：2018-03-15

申请号：US15266214

申请日：2016-09-15

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Haining Yang ,  Jun Yuan ,  Kern Rim ,  Periannan Chidambaram

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/785

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.

公开(公告)号：US12224347B2

公开(公告)日：2025-02-11

申请号：US17180219

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Xia Li ,  Haining Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

公开(公告)号：US20240421157A1

公开(公告)日：2024-12-19

申请号：US18336269

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Ming-Huei Lin ,  Haining Yang

IPC: H01L27/092 ,  H01L21/8238

Abstract: A gate cut extending through a gate adjacent to a channel region of a 3D FET causes the gate to exert a first force and a second force in directions orthogonal to each other on the channel region to improve carrier mobility, thereby increasing drive strength. The gate cut may include a gate cut wall to cause the gate to exert a first force in a first direction on the channel region. The gate cut may include a gate cut wedge to cause the gate to exert a second force in the first direction and exert a third force in a second direction on the channel region to further improve carrier mobility. The 3D FET may be P-type or N-type and the 3D FET may be FinFET or GAA FET.

公开(公告)号：US20240321860A1

公开(公告)日：2024-09-26

申请号：US18189045

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Junjing Bao ,  Hyunwoo Park ,  Kwanyong Lim

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H03K19/0948

CPC classification number: H01L27/0207 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H03K19/0948

Abstract: Logic circuits are implemented in row cell circuits that include diffusion regions. Each diffusion region portion is employed by a transistor in a cell circuit. A current capacity of each transistor depends on a width of the diffusion region portion. A first diffusion region portion and a second diffusion region portion having different widths intersect along an axis, where the diffusion region of a row cell circuit abruptly transitions (e.g., at a square corner) in width. A gate disposed over the diffusion region along the intersection includes a first side on the first diffusion region portion and a second side on the second diffusion region portion. The transition occurring between the first side and the second side of the gate may be achieved by square corner features formed in the diffusion region. Such features were not previously achievable at small technology nodes due to mask pattern limitations.

公开(公告)号：US20210384227A1

公开(公告)日：2021-12-09

申请号：US16895835

申请日：2020-06-08

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Bin Yang ,  Xia Li

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L21/84 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

Abstract: A gate-all-around (GAA) transistor has an insulator on a substrate. The GAA transistor also may have different crystalline structures for P-type work material and N-type work material. The GAA transistor includes one or more channels positioned between a source region and a drain region. The one or more channels, which may be nanowire, nanosheet, or nanoslab semiconductors, are surrounded along a longitudinal axis by gate material. At a first end of the channel is a source region and at an opposite end of the channel is a drain region. To reduce parasitic capacitance between a bottom gate section and a substrate, an insulator is added on the substrate. Further improvements are made in performance of a circuit having both P-type work material and N-type work material by providing different crystalline lattice structures for the work material.

公开(公告)号：US10679994B1

公开(公告)日：2020-06-09

申请号：US16203205

申请日：2018-11-28

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/06

Abstract: Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions are disclosed. In examples herein, diffusion breaks having dimensions asymmetric to each other are provided in different types of diffusion regions in a circuit to increase carrier mobility in semiconductor channels of a semiconductor device formed in different diffusion regions. In examples herein, the circuit includes a P-type and N-type semiconductor device(s) formed in a P-type and an N-type diffusion region(s), respectively, formed in the substrate. Complementary metal oxide semiconductor (CMOS) circuits can be realized from the P-type and N-type semiconductor devices. Diffusion breaks can induce strain in the diffusion regions with a magnitude of the induced strain related to a dimension of the diffusion breaks. As one example, an induced tensile strain may increase carrier mobility in N-type devices and decrease carrier mobility in P-type devices, with induced compressive strain having the opposite effect.

公开(公告)号：US20200098858A1

公开(公告)日：2020-03-26

申请号：US16138170

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Jie Deng

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L27/118 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3065

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

公开(公告)号：US10573748B1

公开(公告)日：2020-02-25

申请号：US16138313

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

公开(公告)号：US10340370B2

公开(公告)日：2019-07-02

申请号：US15371512

申请日：2016-12-07

Applicant: QUALCOMM Incorporated

Inventor： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.