公开(公告)号：US20140252544A1

公开(公告)日：2014-09-11

申请号：US13785502

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yue Li ,  Xiaoming Chen ,  Zhongping Bao ,  Charles D. Paynter ,  Xiaonan Zhang ,  Ryan D. Lane

IPC: H01L49/02

CPC classification number: H01G2/06 ,  H01G4/38 ,  H01G4/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.

Abstract translation: 一些实施方式提供一种半导体器件，其包括第一衬底，耦合到第一衬底的管芯和耦合到第一衬底的一组焊球。 该组焊球被配置成在管芯和第二衬底之间提供电连接。 半导体器件还包括通过第一衬底耦合到管芯的至少一个去耦电容器。 所述至少一个去耦电容器被配置为在所述管芯和所述第二衬底之间提供电连接。 所述至少一个去耦电容器耦合到所述第一衬底，使得所述至少一个去耦电容器位于所述第一衬底和所述第二衬底之间。 在一些实施方案中，第二衬底是印刷电路板（PCB）。 在一些实施方案中，第一衬底是第一封装衬底，第二衬底是第二封装衬底。

公开(公告)号：US20140246753A1

公开(公告)日：2014-09-04

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US09812752B2

公开(公告)日：2017-11-07

申请号：US15218626

申请日：2016-07-25

Applicant: QUALCOMM Incorporated

Inventor： John Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01P1/20 ,  H01P7/06 ,  H01L21/00 ,  H01L27/15 ,  H01L23/66 ,  H01L49/02 ,  H03B5/18 ,  H01P1/201 ,  H01P1/207 ,  H01L23/552 ,  H01L21/48 ,  H01L23/522 ,  H01L23/60 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01P1/207 ,  H01L21/4853 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/60 ,  H01L23/66 ,  H01L24/16 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6627 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/10 ,  H01L2224/16227 ,  H01P1/201 ,  H01P7/06 ,  H01P7/065 ,  H03B5/1817 ,  H05K1/0243

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

公开(公告)号：US09247647B1

公开(公告)日：2016-01-26

申请号：US14484000

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Jung Ho Yoon ,  Xiaonan Zhang ,  Jong-Hoon Lee ,  Young Kyu Song ,  Uei-Ming Jow

IPC: H01L29/00 ,  H05K1/18 ,  H01L23/498 ,  H01L49/02 ,  H03H7/01

CPC classification number: H01L28/40 ,  H01F17/0006 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/116 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4688 ,  H05K2201/094 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/10734 ,  H01L2924/014

Abstract: A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3rd harmonic suppression filter.

Abstract translation: 包括至少一个介电层的封装基板（或印刷电路板），第一电感结构至少部分地位于介电层，第三互连和第二电感结构中。 第一电感器结构包括第一互连，耦合到第一互连的第一通路和耦合到第一通路的第二互连。 第三互连件耦合到第一电感器结构。 第三互连被配置为提供用于接地信号的电路径。 第二电感器结构至少部分地位于电介质层中。 第二电感器耦合到第三互连。 第二电感器结构包括第四互连，耦合到第四互连的第二通路和耦合到第二通路的第五互连。 第一和第二电感器结构被配置为用作为三次谐波抑制滤波器的电容器操作。

公开(公告)号：US20160020193A1

公开(公告)日：2016-01-21

申请号：US14334521

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Jong-Hoon Lee ,  Young Kyu Song ,  Daeik Daniel Kim ,  Jung Ho Yoon ,  Uei-Ming Jow ,  Mario Francisco Velez ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L25/065 ,  H01L25/00 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.

Abstract translation: 一些特征涉及包括衬底，第一管芯，第一封装层，第一再分配部分，第二管芯，第二封装层和第二封装层的集成器件（例如，封装封装（PoP）器件） 第二再分配部分。 基板包括第一表面和第二表面。 基板包括电容器。 第一管芯耦合到衬底的第一表面。 第一封装层封装第一裸片。 第一再分配部分耦合到第一封装。 第二管芯耦合到衬底的第二表面。 第二封装层封装第二管芯。 第二再分配部分耦合到第二封装层。

公开(公告)号：US09035421B2

公开(公告)日：2015-05-19

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US20150048480A1

公开(公告)日：2015-02-19

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US09653533B2

公开(公告)日：2017-05-16

申请号：US14625484

申请日：2015-02-18

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Xiaonan Zhang

IPC: H01L23/52 ,  H01L49/02 ,  H01L23/522 ,  H01G4/33 ,  H01L23/64

CPC classification number: H01L28/86 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

公开(公告)号：US20160372253A1

公开(公告)日：2016-12-22

申请号：US14746652

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Uei-Ming Jow ,  Young Kyu Song ,  Jong-Hoon Lee ,  Jung Ho Yoon ,  Sangjo Choi ,  Xiaonan Zhang

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F17/0006 ,  H01F17/0013 ,  H01F41/041 ,  H01F2027/2809

Abstract: An inductor structure includes a first set of traces corresponding to a first layer of an inductor, a second set of traces corresponding to a second layer of the inductor, and a third set of traces corresponding to a third layer of the inductor that is positioned between the first layer and the second layer. The first set of traces includes a first trace and a second trace that is parallel to the first trace. A dimension of the first trace is different from a corresponding dimension of the second trace. The second set of traces is coupled to the first set of traces. The second set of traces includes a third trace that is coupled to the first trace and to the second trace. The third set of traces is coupled to the first set of traces.

Abstract translation: 电感器结构包括对应于电感器的第一层的第一组迹线，对应于电感器的第二层的第二组迹线，以及对应于电感器的第三层的第三组迹线，其位于 第一层和第二层。 第一组轨迹包括与第一轨迹平行的第一轨迹和第二轨迹。 第一个跟踪的维度与第二个跟踪的相应维度不同。 第二组迹线耦合到第一组迹线。 第二组迹线包括耦合到第一迹线和第二迹线的第三迹线。 第三组迹线耦合到第一组迹线。

公开(公告)号：US09449762B2

公开(公告)日：2016-09-20

申请号：US14272356

申请日：2014-05-07

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu Song ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H05K1/03 ,  H01G4/236 ,  H01G2/02 ,  H05K1/18 ,  H05K1/11 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01G4/224 ,  H05K3/46 ,  H01G2/10 ,  H05K1/02

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。