公开(公告)号：US09035421B2

公开(公告)日：2015-05-19

申请号：US13787219

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Young K. Song ,  Yunseo Park ,  Xiaonan Zhang ,  Ryan D. Lane ,  Babak Nejati ,  Aristotele Hadjichristos ,  Xiaoming Chen

IPC: H01L27/08 ,  H01L23/522 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/117 ,  H01L2224/02375 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Abstract translation: 一些新颖特征涉及第一示例，提供了包括印刷电路板（PCB），焊球和裸片的资产的半导体器件。 PCB包括第一金属层。 该组焊球与PCB相连。 模具通过一组焊球耦合到PCB。 模具包括第二金属层和第三金属层。 PCB的第一金属层，焊球集合，管芯的第二和第三金属层被配置为在半导体器件中作为电感器工作。 在一些实施方式中，芯片还包括钝化层。 钝化层位于第二金属层和第三金属层之间。 在一些实施方案中，第二金属层位于钝化层和一组焊球之间。

公开(公告)号：US10262786B2

公开(公告)日：2019-04-16

申请号：US15288967

申请日：2016-10-07

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Babak Nejati ,  Husnu Ahmet Masaracioglu

IPC: H03H7/01 ,  H03H7/46 ,  H01F17/00 ,  H01F27/28 ,  H01F41/04 ,  H01L49/02 ,  H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H03H1/00

Abstract: A stepped-width, co-spiral inductor structure includes a first exterior layer having a first exterior width. The stepped-width, co-spiral inductor structure also includes a first interior layer coupled to the first exterior layer. The first interior layer includes a first interior width that is wider than the first exterior width of the first exterior layer. The stepped-width, co-spiral inductor structure further includes a second exterior layer coupled to the first interior layer. The second exterior layer includes a second exterior width that is narrower than the first interior width of the first interior layer.

公开(公告)号：US11380471B2

公开(公告)日：2022-07-05

申请号：US16034653

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Bonhoon Koo ,  Babak Nejati

IPC: H01F27/28 ,  H01F17/02 ,  H03F1/08 ,  H01F17/00 ,  H03F3/19 ,  H03F3/21

Abstract: A spiral inductor includes a spiral trace and a plurality of first projections extending along a first edge of the spiral trace. The spiral inductor may further include a plurality of second projections extending along a second edge of the spiral trace, the second edge being opposite the first edge.

公开(公告)号：US10832848B2

公开(公告)日：2020-11-10

申请号：US15722446

申请日：2017-10-02

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Bonhoon Koo ,  Babak Nejati

IPC: H01F17/00 ,  H01F41/04 ,  H05K1/16 ,  H01F27/28 ,  H05K3/46

Abstract: A multi-layer spiral inductive array includes a first multi-layer spiral inductor with a second layer matching a spiral pattern of a first layer. The multi-layer spiral inductive array also includes a second multi-layer spiral inductor with a third layer matching a spiral pattern of a fourth layer. The second multi-layer spiral inductor is coupled in series with the first multi-layer spiral inductor.

公开(公告)号：US11011461B2

公开(公告)日：2021-05-18

申请号：US16254735

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Shu Zhang ,  Daniel Daeik Kim ,  Chenqian Gan ,  Bonhoon Koo ,  Babak Nejati

IPC: H01L23/522 ,  H01L49/02 ,  H01F27/28 ,  H01F41/04 ,  H01L23/64 ,  H01F17/02 ,  H01F17/00 ,  H01L23/498

Abstract: Some features pertain to a substrate, and a first inductor integrated into the substrate. The first inductor includes a plurality of first inductor windings in a first metal layer and a second metal layer. A second inductor is integrated into the substrate. The second inductor includes a first spiral in a third metal layer. The first spiral is located at least partially inside the plurality of first inductor windings, wherein the second inductor is perpendicular to the first inductor.

公开(公告)号：US10978240B2

公开(公告)日：2021-04-13

申请号：US15857478

申请日：2017-12-28

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Babak Nejati ,  Husnu Ahmet Masaracioglu

IPC: H01F27/29 ,  H01F27/28 ,  H01F41/04 ,  H05K1/02 ,  H01F17/00 ,  H05K1/16 ,  H01F5/00 ,  H04B1/00 ,  H04B1/40 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42

Abstract: A laminate substrate inductor reduces insertion loss and improves isolation while reducing the area for integrating the laminate substrate inductor. The laminate substrate includes a spiral trace. The laminate substrate also includes a first capture pad at a first end of the spiral trace. The first end is located at a corner of the spiral trace. The first capture pad is substantially within a bounding box of the spiral trace. At least a portion of the first capture pad and an outer edge of the spiral trace have a same distance from a ground.

公开(公告)号：US20190189327A1

公开(公告)日：2019-06-20

申请号：US16210594

申请日：2018-12-05

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Bonhoon Koo ,  Babak Nejati

IPC: H01F17/00 ,  H01F41/04 ,  H04B1/40

CPC classification number: H01F17/0013 ,  H01F27/365 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/008 ,  H04B1/40

Abstract: A vertical inductor structure includes a first laminate substrate forming a first portion of the vertical inductor structure and a second laminate substrate forming a second portion. Each laminate substrate includes a plurality of first traces embedded in a layer of the laminate substrate, a plurality of first vertical columns, and a plurality of second vertical columns. Each first vertical columns is coupled to a first end of a respective first trace, and each second vertical column is coupled to a second end of a respective first trace. The second laminate substrate is mounted on the first laminate substrate such that each first vertical column of the first laminate substrate is coupled to a respective first vertical column of the second laminate substrate, and each second vertical column of the first laminate substrate is coupled to a respective second vertical column of the second laminate substrate.

公开(公告)号：US20150171800A1

公开(公告)日：2015-06-18

申请号：US14109239

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Aristotele Hadjichristos ,  Calogero Davide Presti ,  Babak Nejati

IPC: H03F1/56 ,  H03F3/19

CPC classification number: H03F1/565 ,  H03F3/19 ,  H03F3/191 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/111 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/417 ,  H03F2200/423

Abstract: A tunable loadline is disclosed. In an exemplary embodiment, an apparatus includes an amplifier configured to output an amplified signal having a selected power level and a first impedance network coupled to receive the amplified signal at an input terminal and generate a first output signal having a first power level at a first output terminal. The first impedance network being configured to load the amplified signal to convert the selected power level to the first power level. The apparatus also includes a second impedance network configured to selectively receive the first output signal and generate a second output signal having a second power level at a second output terminal. The second impedance network being configured to combine with the first impedance network to load the amplified signal to convert the selected power level to the second power level.

Abstract translation: 公开了一种可调节负载线。 在示例性实施例中，一种装置包括：放大器，被配置为输出具有选定功率电平的放大信号和耦合以在输入端接收放大信号的第一阻抗网络，并产生第一功率电平的第一输出信号 输出端子。 第一阻抗网络被配置为加载放大的信号以将所选择的功率电平转换为第一功率电平。 该装置还包括配置成选择性地接收第一输出信号并且在第二输出端产生具有第二功率电平的第二输出信号的第二阻抗网络。 第二阻抗网络被配置为与第一阻抗网络组合以加载放大的信号以将所选择的功率电平转换为第二功率电平。

公开(公告)号：US11817239B2

公开(公告)日：2023-11-14

申请号：US16210594

申请日：2018-12-05

Applicant: QUALCOMM Incorporated

Inventor： Daniel Daeik Kim ,  Bonhoon Koo ,  Babak Nejati

IPC: H01F27/36 ,  H01F17/00 ,  H01F41/04 ,  H04B1/40 ,  H04B1/04

CPC classification number: H01F17/0013 ,  H01F27/363 ,  H01F41/041 ,  H04B1/40 ,  H01F27/36 ,  H01F2017/002 ,  H01F2017/008 ,  H04B1/04

Abstract: A vertical inductor structure includes a first laminate substrate forming a first portion of the vertical inductor structure and a second laminate substrate forming a second portion. Each laminate substrate includes a plurality of first traces embedded in a layer of the laminate substrate, a plurality of first vertical columns, and a plurality of second vertical columns. Each first vertical columns is coupled to a first end of a respective first trace, and each second vertical column is coupled to a second end of a respective first trace. The second laminate substrate is mounted on the first laminate substrate such that each first vertical column of the first laminate substrate is coupled to a respective first vertical column of the second laminate substrate, and each second vertical column of the first laminate substrate is coupled to a respective second vertical column of the second laminate substrate.

公开(公告)号：US10431511B2

公开(公告)日：2019-10-01

申请号：US15584000

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Shu Zhang ,  Bonhoon Koo ,  Manuel Aldrete ,  Jie Fu ,  Chin-Kwan Kim ,  Babak Nejati ,  Husnu Ahmet Masaracioglu

IPC: H01L23/12 ,  H01L23/66 ,  H01L23/498 ,  H01L23/552

Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.