公开(公告)号：US20160276576A1

公开(公告)日：2016-09-22

申请号：US15170851

申请日：2016-06-01

Applicant: QUALCOMM Incorporated

Inventor： William H. XIA ,  Wenqing WU ,  Kendrick H. YUEN ,  Abhishek BANERJEE ,  Xia LI ,  Seung H. KANG ,  Jung Pill KIM

IPC: H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/08 ,  H01L43/12

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract translation: 存储单元包括耦合到磁隧道结（MTJ）结构的细长第一电极和与耦合到MTJ结构的细长第一电极对准的细长第二电极。 细长电极被配置为引导开关电流感应磁场的相互添加部分通过MTJ。 响应于开关电流的应用，相互添加的部分增强MTJ的切换。

公开(公告)号：US20160020250A1

公开(公告)日：2016-01-21

申请号：US14334554

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Wei-Chuan CHEN ,  Yu LU ,  Kangho LEE ,  Seung Hyuk KANG

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/224 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/73 ,  H01L27/228 ,  H01L43/08

Abstract: An MRAM cell may include a magnetic tunneling junction (MTJ). The MTJ includes a pin layer, a barrier layer, a free layer, and a capping layer. The MRAM cell further includes a bidirectional diode selector, directly coupled to an electrode of the MTJ, to enable access to the MTJ.

Abstract translation: MRAM单元可以包括磁隧道结（MTJ）。 MTJ包括针层，阻挡层，自由层和覆盖层。 MRAM单元还包括直接耦合到MTJ的电极的双向二极管选择器，以使得能够访问MTJ。

公开(公告)号：US20150333072A1

公开(公告)日：2015-11-19

申请号：US14280213

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Daniel Wayne PERRY

IPC: H01L27/112 ,  G11C7/00 ,  G11C11/40

CPC classification number: H01L27/112 ,  G11C7/00 ,  G11C11/40 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract translation: 提供先进的金属氮化物 - 氧化物 - 硅（MNOS）多时间可编程（MTP）存储器。 在一个示例中，装置包括两个场效应晶体管（2T场FET）金属氮化物 - 氧化物 - 硅（MNOS）MTP存储器。 2T场FET MNOS MTP存储器可以包括形成在阱上的层间电介质（ILD）氧化物区域，并将第一和第二晶体管的相应栅极与阱分离。 控制栅极位于第一和第二晶体管的各个栅极之间，并且氮化硅 - 氧化物（SiN）区域位于控制栅极的金属部分和ILD氧化物区域的一部分之间。

公开(公告)号：US20150311429A1

公开(公告)日：2015-10-29

申请号：US14795799

申请日：2015-07-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kangho LEE ,  Wei-Chuan CHEN ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种用于制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：US20150280112A1

公开(公告)日：2015-10-01

申请号：US14229427

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kangho LEE ,  Wei-Chuan CHEN ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

公开(公告)号：US20150249209A1

公开(公告)日：2015-09-03

申请号：US14195566

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Xia LI ,  Seung Hyuk KANG ,  Shiqun GU

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。

公开(公告)号：US20250072105A1

公开(公告)日：2025-02-27

申请号：US18455511

申请日：2023-08-24

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Junjing BAO ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: An integrated circuit (IC) device includes an N-type field effect transistor (FET). The N-type FET includes an N-type vertical structure on a substrate, including an N-type gate region having a first normal-k oxide layer on a semiconductor layer of the N-type vertical structure, an N-type work-function metal (WFM) layer on the first normal-k oxide layer and sidewall spacers of the N-type gate region, and a first metal gate on the N-type WFM layer. The IC device includes a first P-type FET. The first P-type FET includes a first P-type vertical structure on the substrate, including a first P-type gate region having a second normal-k oxide layer on a first semiconductor layer of the first P-type vertical structure, a first P-type WFM layer on the second normal-k oxide layer and sidewall spacers of the first P-type gate region, and a second metal gate on the first P-type WFM layer.

公开(公告)号：US20240421214A1

公开(公告)日：2024-12-19

申请号：US18334301

申请日：2023-06-13

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kwanyong LIM ,  Haining YANG ,  Biswa Ranjan PANDA ,  Ramesh MANCHANA

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A field effect transistor (FET) is described. The FET includes a substrate, having a first vertical structure on the substrate, including a source/drain region having a first stressor material. The FET also includes a second vertical structure on the substrate and including a drain/source region having a second stressor material different from the first stressor material. The FET further includes a metal gate on the first vertical structure and on the second vertical structure.

公开(公告)号：US20240105688A1

公开(公告)日：2024-03-28

申请号：US17952163

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xuefeng ZHANG ,  Aniket PATIL

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/182 ,  H01L2924/37001

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects, a first chiplet coupled to the substrate, a second chiplet coupled to the first chiplet, an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet, a plurality of encapsulation interconnects located in the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects and a first integrated device coupled to the metallization portion.

公开(公告)号：US20220293513A1

公开(公告)日：2022-09-15

申请号：US17198941

申请日：2021-03-11

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Haining YANG

IPC: H01L23/522 ,  H01L21/8234 ,  H02J50/05 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528

Abstract: Disclosed are examples of a device including a front side metallization portion having a front side BEOL. The device also includes a backside BEOL. The device also includes a substrate, where the substrate is disposed between the backside BEOL and the front side metallization portion. The device also includes a metal-insulator-metal (MIM) capacitor embedded in the backside BEOL.